Hi all,
Question on the clock routing in a Virtex 4 LX 25 that I haven't found the answer to today.
I have an input clock, single ended, on a clock pin in the top half of the centre slice of the die. This clock has a IBUFG instantiated and is then connected to the clkin pins on two DCMs locked into the top half of the die and a BUFG which drives some clock monitor logic.
The routing from the input buffer to the BUFG is on nice global pink (in fpga_editor) clock net, but the route to my two DCMs is on a normal general purpose net which Ts off this. Normally it is pretty direct, but depending on the build it sometimes goes through a couple of switch boxes. I am trying to stop this!
I put a skew constraint on this net hoping to force it onto a global bus, but it just failed the constraint (~560 pS skew, 1.2nS delay to DCM pin if I remember correctly)
The clock phase is important as I am sampling a DDR input bus, and I discovered this variation when I put some offset constraints on the input pins relative to phase shifted DCM output clock generated from this net.
I thought the problem may be caused by having a BUFG on the same net, but removing this does not have any effect.
I thought the software would use a direct connect from the IBUFG to the DCM input, and then adjust the phase of the DCM to compensate for the delay. (I am using a variable phase DCM here to dynamically tune my timing, is the routing delay from the IBUF a fixed offset???)
If the routing is varing so much, is my input delay really being compensated? Perhaps it is the fact I am driving two DCMs which is breaking it, but I am a bit stuck with this?
Using ISE software 9.1 sp3.
Any thoughts anyone? Cheers, Mike.