Hi everybody, In the new version (2.1) of the Virtex-4 User Guide (ug070), in the FIFO chapter is described the synchronous clock work-around (page 161) to solve the FIFO bug. At the end of the paragraph the following is written: "The connections between the input registers and the FIFO16 must be tightly constrained, as this part of the circuit effectively runs at twice the clock rate." Can anybody explain me which contraints are needed? placement? timing? an example is wellcome!
Thanks Mehdi
Because one is posedge and the other negedge, signals only have half a period to get from the FFs' outputs to the FIFOs' inputs. At 100MHz, this is not really a problem but at 200MHz and beyond, this translates to less than 2.5ns timing constraints. Unless those work-around FFs are constrained very close to the FIFOs, PAR is going to take forever to meet timings and might fail altogether.
If you use CoreGen to generate these FIFOs, you can give it read/write frequencies.
CoreGen creates RPMs (relationaly placed macros) so the design coregen gives you should meet timing, because the placement has already been done and the placement tool shouldn't touch it...
That being said.... there are numerous reasons why coregen isn't helpful.. as far as i've found, the primary reason is if you need a fifo that's bigger than
18k. When they added the work around for this hardware flaw (fifo generator 3.2 i think?) they seem to have disabled the ability to use cascaded FIFOs. So if you want to do this, you need to instantiate primitives (unless you're willing to take the resource and performance hit of just casading coregen blocks and implementing many more resource hungry "patches" than you really need) , implement the work around by hand, and constrain your half-period paths appropriately....yeaup... pretty much a pain in the rear either way.... between this patch and the fact that there's no true "1 word left" almost empty flag (or almost full flag), I think Xilinx royally messed up on the FIFO16 block.... Just using straight block ram FIFOs takes just a few more resources than the patch (especially if you're using independent read/write clocks - that patch is HUGE) AND gives you all the normal FIFO flags....
On Apr 10, 6:33=C2=A0am, "GaLaKtIkUs=E2=84=A2" wro= te:
ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.