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Virtex-4 BiDirectional Ports

How does one properly synthesize and simulate a bidirectional port on the Virtex-4 using ISE 7.1i.

I drafted code from an earlier Spartan 3 design, which synthesized nicely. On the Virtex-4, the T signals is not registered although the block diagram indicates that it could be.

Also, the ISE simulator does not show any output values on the inout ports.

Thanks,

Brad Smallridge

sram_tristate_process:process(sram_clk) begin if( sram_clk'event and sram_clk='1') then if( sram_cam_en_2='1' ) then sram_flash_data

Reply to
Brad Smallridge
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Brad - I also haven't figured out how to simulate a bi-directional port using ISE. The code below is basically what I've used for a bi-directional register.

write_reg: process ( clk ) is begin if rising_edge( clk ) then if reg_sel = '1' and write = '1' then my_reg

Reply to
Dave Pollum

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