Hi, there:
Does "bitgen -r initial.bit second.ncd" generate correct runtime reconfiguration bitstreams?
If I am not wrong, even though I followed the modular approach, there was still slight differences in the fixed module area between the two assemblies...basically the DCMs and BUFGMUX... meaning the difference bitstream might cause problems...
Thanks for your advice...
kelvin
All messages from thread Message 1 in thread From: Ryan Fong ( snipped-for-privacy@vt.edu) Subject: Virtex 2: Partial Bitstream Generation
View this article only Newsgroups: comp.arch.fpga Date: 2002-04-23 07:50:56 PST
Is it possible to generate partial bitstreams using the Xilinx ISE 4.2i tools, without using the Modular Design tools? I am interested in run-time partial reconfiguration to change areas of an FPGA while keeping others areas unchanged.
Thanks.
Message 2 in thread From: Austin Lesea ( snipped-for-privacy@xilinx.com) Subject: Re: Virtex 2: Partial Bitstream Generation
View this article only Newsgroups: comp.arch.fpga Date: 2002-04-24 07:46:14 PST
Ryan,
Here is the answer from the expert:
"Hi Austin, The -r switch is currently a hidden switch, but it will be visible in the next major release. The switch will make bitgen read in an existing bitstream, and then when the bitstream for the new design is created, only the frames that are different between the two bitstreams will be written.
The -r switch takes a bitstream as an argument. An example command line would be:
$ bitgen -w -r old.bit new.ncd
The -r switch is useful if you have a limited number of possible reconfigurations."
Austin
Ryan F> Is it possible to generate partial bitstreams using the Xilinx ISE 4.2i
tools, without using the Modular Design tools? I am interested in run-time partial reconfiguration to change areas of an FPGA while keeping others areas unchanged.
Message 3 in thread From: Martin Subject: Re: Virtex 2: Partial Bitstream Generation
View this article only Newsgroups: comp.arch.fpga Date: 2002-05-07 08:02:44 PST
Hi Ryan,
brief answer: No, you can't.
The partial reconfiguration flow is a subset of the Modular Design flow. For each of the reconfiguration-modules you need to run the implementation on the single module. After you have the implementation data for each module you'll need to stitch the files together and create the initial and partial bitstreams. The latter one can be done either by comparing the bitstreams which each other and creating small bit-streams with only the differences or you can create the re-configuration bitstream from the floorplanning-information.
From the timing point of view you can save yourself quite some time for the re-configuration of the device. I did a test once with a Virtex-E 600 and a MultiLINX Cable on the serial port (slowest BAUD-rate). The complete configuration took about 1.5 minutes. Re-configuration with a small bit-stream took about 8 seconds. As you can see there can be quite a difference in configuration time. (BTW: Normal Configuration via MultiLINX and USB took about 13 seconds, re-configuration was only a glimpse.)
but as you can surely imagine, the time for re-configuration is very dependend on the changes you are doing. If you are only doing minor changes re-configuration will be quicker than if you'd do major changes.
Martin
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