How can the RTL schematic of a VHDL design be viewed in Xilinx ISE 9.2? I just upgraded from 8.2 because I couldn't find it there (and the upgrade was long due anyway), but I still have not found it.
I have searched the web and all references to viewing RTL schematic seem to point to 7.x documentation. Using that method is not possible because the options are not there anymore in 8.2/9.2.