Let me try that again. Quoting from Micron's SDRAM (SDR, not DDR) data sheet: "The addressing is generated by the internal refresh controller. This makes the address bits "Don't Care" during an AUTO REFRESH command. The 64Mb SDRAM requires 4,096 AUTO REFRESH cycles every 64ms (EF), regardless of width option."
Which suggests that for this SDR SDRAM, a frame rate of 15 Hz or higher is enough to keep all displayed pixels refreshed. DDR SDRAM is probably very similar. Your 1/8 ~ 1/4 s is much too slow.
You have to precharge a bank only when you switch to another row within that bank.
That very much depends on the access patterns. The fact that you are going to implement a frame buffer alone doesn't automatically mean that you won't need a refresh. Double-, or triple-check your specs. If in doubt I'd definitely recommend putting in a refresh as low priority task.
Regards, Marcus
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First of all, you don't "switch" banks. There are four banks that can all potentially be active at a given time. Only the external interface works on one bank at a time. That being said, realise that the control interface (address, ras, cas, we) is somewhat independent of the data interface (dq).
You need to precharge a bank before opening a new row in _THAT_ bank. Other banks may remain open while this happens. When doing single burst accesses, I generally precharge using the read or write command with auto-precharge (A10 high during CAS).
What's a page? These RAMs have rows. Each row must be accessed using row activate or else refreshed within the refresh period. If you store data in successive rows / banks first, and then successive columns (i.e. row/bank form LSB's of your address), you will usually refresh the entire part without accessing a large portion of the entire memory.
Here's a typical sequence I use for writing streaming data into an SDRAM:
Cycle Command Bank Addr Data startup sequence has unused cycles (NOPs) 1 ACT 0 row0 x 2 NOP x x x 3 ACT 1 row0 x 4 NOP x x x 5 ACT 2 row0 x full streaming starts here (burst size = 2) 6 WRITEA 0 col0 data0 7 ACT 3 row0 data0 8 WRITEA 1 col0 data1 9 ACT 0 row1 data1 10 WRITEA 2 col0 data2 11 ACT 1 row1 data2 12 WRITEA 3 col0 data3 13 ACT 2 row1 data3 14 WRITEA 0 col0 data4 15 ACT 3 row1 data4 16 WRITEA 1 col0 data5 above sequence (streaming can be repeated ad nauseum) end sequence has unused cycles (NOPs) 17 NOP x x data5 18 WRITEA 2 col0 data6 19 NOP x x data6 20 WRITEA 3 col0 data7 21 NOP x x data7
WRITEA is write command with autoprecharge (A10 = 1)
Reading is similar except there are pipeline delays on the data bus due to CAS read access time.
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