I did a VHDL program and now I'm downloading the program into a Spartan2 XC2S100PQ208 chip . I ran all the programs ( FC2.... ) and now I'm stucked at the Xilinx FLow Engine . Below is the ucf file .
----------------------------------------------------------------------------- NET "clk" LOC = "P43"; NET "pre" LOC = "P41"; NET "seg" LOC = "P37"; NET "seg" LOC = "P36"; NET "seg" LOC = "P35"; NET "seg" LOC = "P34"; NET "seg" LOC = "P33"; NET "seg" LOC = "P30"; NET "seg" LOC = "P29"; NET "seg" LOC = "P23"; NET "seg" LOC = "P22"; NET "seg" LOC = "P21"; NET "seg" LOC = "P18"; NET "seg" LOC = "P17"; NET "seg" LOC = "P16"; NET "seg" LOC = "P15"; NET "seg" LOC = "P14"; NET "seg" LOC = "P10"; NET "seg" LOC = "P8"; NET "seg" LOC = "P7"; NET "seg" LOC = "P5"; NET "seg" LOC = "P4"; NET "seg" LOC = "P3";
I ran the Implementation and I encounted an Error . It stated :
ERROR: MapLib:93 - Illegal LOC on Symbol "clk.PAD"( Pad signal = clk ) or BUFGP Symbol "C123962" (output signal = clk_BUFGPed ), IPAD-IBUFG should only be LOCed to GCLKIOB site .
What does it mean ? I was wondering if I stated the outputs ( NET " seg" , NET " seg" , NET " seg") wrongly ? Can anyone help me ? Thanks a lot .
Below is my VHDL Electronic Dice ( 3 die ) program .
---------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;
entity dice is port( clk,pre : in std_logic; //inputs seg: out std_logic_vector (20 downto 0)); //outputs end dice;
architecture archdice of dice is type dice_states is (s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,s11,s12,s13,s14,s15,s16,s17,s18,s19, s20,s21,s22,s23,s24,s25,s26,s27,s28,s29,s30,s31,s32,s33,s34,s35,s36, s37,s38,s39,s40,s41,s42,s43,s44,s45,s46,s47,s48,s49,s50,s51,s52,s53, s54,s55,s56,s57,s58,s59,s60,s61,s62,s63,s64,s65,s66,s67,s68,s69,s70, s71,s72,s73,s74,s75,s76,s77,s78,s79,s80,s81,s82,s83,s84,s85,s86,s87, s88,s89,s90,s91,s92,s93,s94,s95,s96,s97,s98,s99,s100,s101,s102,s103, s104,s105,s106,s107,s108,s109,s110,s111,s112,s113,s114,s115,s116,s117, s118,s119,s120,s121,s122,s123,s124,s125,s126,s127,s128,s129,s130,s131, s132,s133,s134,s135,s136,s137,s138,s139,s140,s141,s142,s143,s144,s145, s146,s147,s148,s149,s150,s151,s152,s153,s154,s155,s156,s157,s158,s159, s160,s161,s162,s163,s164,s165,s166,s167,s168,s169,s170,s171,s172,s173, s174,s175,s176,s177,s178,s179,s180,s181,s182,s183,s184,s185,s186,s187, s188,s189,s190,s191,s192,s193,s194,s195,s196,s197,s198,s199,s200,s201, s202,s203,s204,s205,s206,s207,s208,s209,s210,s211,s212,s213,s214,s215,s216); signal sm: dice_states; begin
process (clk,pre) begin if pre = '1' then sm