Hi, all , I use syplify to synthesize the following vhdl. it comes out with warnings for signal BitSync_temp, pnt. It seems from the coding logic it can't have the mux problem since the assignment conditions exclude each other...(to my understanding), could you give me some comments , thanks first.
Warning: @W: CL113 : Feedback mux created for signal BitSync_temp. @W: CL113 : Feedback mux created for signal pnt[6:0].
process(Clk, Reset,MaxSearchEn) variable pnt : std_logic_vector(6 downto 0); -- integer range 87 downto
0; 88= 101 1000 begin if (Reset = '1') then pnt := (others => '0'); BitSync_temp