VHDL warning " Feedback mux " from synplify pro ...thx

Hi, all , I use syplify to synthesize the following vhdl. it comes out with warnings for signal BitSync_temp, pnt. It seems from the coding logic it can't have the mux problem since the assignment conditions exclude each other...(to my understanding), could you give me some comments , thanks first.

Warning: @W: CL113 : Feedback mux created for signal BitSync_temp. @W: CL113 : Feedback mux created for signal pnt[6:0].

process(Clk, Reset,MaxSearchEn) variable pnt : std_logic_vector(6 downto 0); -- integer range 87 downto

0; 88= 101 1000 begin if (Reset = '1') then pnt := (others => '0'); BitSync_temp
Reply to
Jimmy
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You don't really want the process sensitive to events on MaxSearchEn, I assume that signal is meant to be a clock enable.

Regards, Allan.

Reply to
Allan Herriman

Also, your clock enabled processes should look something like:

label : process(clk, reset) begin if reset = '1' then ... elsif rising_edge(clk) then if clk_enable = '1' then ... end if; end if; end process;

Comments:

  1. You don't need () around the condition in an IF statement. You're not writing C (or Verilog)!

  1. rising_edge(clk) is a lot clearer than clk'event and clk='1'. There are some minor semantic differences that probably won't worry you.

  2. Use separate IF statements for the rising_edge and clk_enable parts. It's easier to read, and some synthesisers may have problems if they're combined into the one condition.

  1. VHDL doesn't force you to label processes, but I find it makes it easier to read the code if they are labeled, assuming you choose labels sensibly.

Regards, Allan.

Reply to
Allan Herriman

That structure makes an implied memory element for bitsync_temp in the case pnt

Reply to
Ray Andraka

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