VHDL-Verilog Co-Simulation

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I have my design files in Verilog,but want to have my
testbenches in VHDL.I think this is possible.
Can anybody suggest some pointers to this.
I am using ModelSim 5.7g and Xilinx Project Navigator 6.2.


Re: VHDL-Verilog Co-Simulation

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No problem, as long as you have the (expensive) Modelsim license that
allows co-simulation.  Check your license.


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