VHDL Variable Length Input file.

I have a test bench in which the input stimulus file length is unknown.

I would like to read the file in to my test bench and loop through each element of the stimulus every clock. The only problem is the the upper limit of the loop is unknown. I created the following to find the file length (number of elements) and use that length as the upper limit of a loop used to read the file into an array which is based off of that length. Here is the code I created (shortened for posting) but

it doesn't work in Model Sim:

. . . signal ind : integer range 1 to 16777216;

--

-- Determine length of input file

--

filelength : process

variable index : integer :=3D 0; variable linein : line; variable test : integer; file f2 : text open READ_MODE is "adc.txt";

begin

while not (endfile(f2)) loop readline(f2,linein); read(linein,test); index :=3D index + 1; end loop;

ind

ted a écrit :

You can not do it that way. You will need to use dynamic allocation with pointers (access type)

Nicolas