VHDL: Use of literal '1' on an input port ?

Hello all,

I'm still working with DSPBuilder. Here's a VHDL problem that I can fix but don't understand. DSPBuilder.vhd has a line

obj:lpm_add_sub port map (cin => '1');

Quartus is happy with this, and in fact I use constant port values in my own VHDL all the time. But Model Technology (Altera Edition 5.7e) complains:

# ** Error: Actual for formal cin is not a signal. # ** Error: Value associated with cin does not have a static name.

So first I tried

constant one : std_logic := '1'; ... obj:lpm_add_sub port map (cin => one);

and got # ** Error: Actual for formal cin is not a signal.

And finally

signal one : std_logic := '1'; ... obj:lpm_add_sub port map (cin => one);

which worked.

My questions are:

(1) Why is port map(cin=>'1') not considered OK ?

(2) Is it bad practice to do this ?

Thanks in advance for any pointers.

Btw, The component declaration for lpm_add_sub is

COMPONENT lpm_add_sub GENERIC ( ); PORT ( cin: IN STD_LOGIC := '0'; ); END COMPONENT;

-rajeev-

Reply to
Rajeev
Loading thread data ...

Rajeev, Make sure to turn on the VHDL-93 switch.

You can do this in the compile options menu item under compile in 5.7.

Cheers, Jim

--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
 Click to see the full signature
Reply to
Jim Lewis

Jim,

Thanks much ! That did it.

-rajeev-

Reply to
Rajeev

Why do you suppose Modelsim defaults to -93 off? Perhaps someone should report this as a bug.

Allan.

Reply to
Allan Herriman

In Modelsim 5.8 it defaults to VHDL 2002, so I guess your wish is granted :-)

regards Alan

--
Alan Fitch
Consultant
 Click to see the full signature
Reply to
Alan Fitch
[...]

It doesn't any more - since about version 5.8, the default has been VHDL-2001.

Hardly a "bug", when you can fix it by deleting just one comment character in the modelsim.ini file :-) But I have been known to call it a "bloody nuisance".

--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
 Click to see the full signature
Reply to
Jonathan Bromley

All tool vendor decisions like this are market driven (as opposed to standards driven).

It was VHDL -87 because for a long time because the majority of designs were done in ASICs and their users wanted the default to match what the market leader (at the time) of ASIC synthesis (Synopsys) could handle at the time.

Now the majority of designs are done in FPGAs. The market leaders of the FPGA synthesis market seem to support current language features.

So now by market request it changes to -2002, something much more useful.

So the market driven picture is this. A vendor will not invest in new language features out of good will. They will invest only by market (user) request. So as VHDL (and Verilog/SV) evolve, if you see a feature you want, make sure to tell your EDA vendor you want it. This is particularly effective around the time you are renewing licenses - they seem to listen better to $$$.

Cheers, Jim

--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
 Click to see the full signature
Reply to
Jim Lewis

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.