Hello all,
I'm still working with DSPBuilder. Here's a VHDL problem that I can fix but don't understand. DSPBuilder.vhd has a line
obj:lpm_add_sub port map (cin => '1');
Quartus is happy with this, and in fact I use constant port values in my own VHDL all the time. But Model Technology (Altera Edition 5.7e) complains:
# ** Error: Actual for formal cin is not a signal. # ** Error: Value associated with cin does not have a static name.
So first I tried
constant one : std_logic := '1'; ... obj:lpm_add_sub port map (cin => one);
and got # ** Error: Actual for formal cin is not a signal.
And finally
signal one : std_logic := '1'; ... obj:lpm_add_sub port map (cin => one);
which worked.
My questions are:
(1) Why is port map(cin=>'1') not considered OK ?
(2) Is it bad practice to do this ?
Thanks in advance for any pointers.
Btw, The component declaration for lpm_add_sub is
COMPONENT lpm_add_sub GENERIC ( ); PORT ( cin: IN STD_LOGIC := '0'; ); END COMPONENT;
-rajeev-