vhdl type conversions

hi

can anybody help me out with my problem please: i have a custom type:

type STATE_TYPE is (Idle, Read_Config, Read_Data, Generate_Address, Generate_Strobe, Write_Data); signal state : STATE_TYPE;

for debugging purposes i want to route the signal state out of the fpga. for that i have a signal dbg_state std_logic_vector(2 downto 0) in my portmap. but of course the statement dbg_state

Reply to
u_stadler
Loading thread data ...

Try: case state is when Idle => dbg_state dbg_state dbg_state dbg_state dbg_state dbg_state NULL; end case;

Reply to
manfredk

(1) Try comp.lang.vhdl instead. (2) Write a function to do the type conversion - it makes life far easier in the long run - and use a case statement inside that function:

subtype slv3 is std_logic_vector(2 downto 0); function to_slv3(s: state_type) return slv3 is begin case s is when idle => return "000"; when read_config => return "001"; ....etc.... end case; end;

And then you can simply drive the output...

dbg_state "000", read_config => "001", ... );

And then you can use that lookup table like a conversion function:

dbg_state state_dbg, ... );

Constant lookup tables are extremely efficient, and the code for them is extremely easy to write and maintain, but you can't use them in a port map as you can a conversion function.

HTH

--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which 
are not the views of Doulos Ltd., unless specifically stated.
Reply to
Jonathan Bromley

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; ... function mode2vec (arg : STATE_TYPE) return std_logic_vector is begin return std_logic_vector( to_unsigned(STATE_TYPE'pos(arg),3) ); end function mode2vec; ... dbg_state

Reply to
Mike Treseler

dbg_state

Reply to
KJ

Reply to
Jonathan Bromley

thanks for all the answers! just tried it and yes it works in ise too!

Urban Stadler

Reply to
u_stadler

Thanks for reporting the results.

-- Mike Treseler

Reply to
Mike Treseler
[I wrote:]
[VHDL 'pos and 'val attributes]

No, indeed I don't.

If I say (truthfully) "tools A and B support feature F", and it happens that tool C also supports feature F, then vendor C is quite likely to give my employer a hard time for the perceived unfair publicity. I would much prefer to say "some tools support feature F", and allow people to find out for themselves from their chosen (or candidate) vendors if it matters to them.

If I were to get involved in "who supports what" feature comparisons, I would be duty bound to be far more thorough and careful than would ever be possible in a newsgroup posting. In particular, I would need to prepare my comparisons and submit them to all the vendors before publication so that they could correct any factual inaccuracies before going to press.

I have no desire to be a stooge of any of the tool vendors, but it is also very important to me and to my employer that we treat them all fairly. We cannot avoid discussing specific tools as part of our training courses, and we must scrupulously avoid bias.

By contrast, a customer of one single vendor has (almost) no such obligation of impartiality and, give or take a few legalistic constraints, can say whatever they want about the tool they have purchased.

Sorry to disappoint :-)

--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which 
are not the views of Doulos Ltd., unless specifically stated.
Reply to
Jonathan Bromley

Fair enough. Please do keep posting the clever hdl ideas. We'll dish the reviews.

I would suggest that designers maintain a non-proprietary module/entity that covers all of the hdl features considered important. Doing this makes it much easier for me to evaluate new tools or new revisions of old tools. It is also makes quick work of writing a bug report when I can freely attach the code and error message.

-- Mike Treseler

Reply to
Mike Treseler

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