VHDL to create LUT based delay

I'm looking to create a LUT based delay line for use in aligning DDR strobes. The target device is a V2P, I have read the application notes provided by Xilinx on this topic but can't seem to find a reference design that illustrates this usage of LUTs. Perhaps someone could point me in the right direction.

Thanks in advance,

Brendan

Reply to
Brendan Illingworth
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Hi,

in general it is a bad practise to align the signal via such delay. So I would recommend to think more about synchronisation of your design (e.g. add addition flops). If you still want to do it (if i correctly understand), you would have to constraint LUTs so the synthesiser will not optimise them away. Regards Alex

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Alex
Reply to
Alex

Brendan, use Virtex-4 instead. There you have the IDELAY that gives you sub-100 picosecond granularity on the input side, and stability over temperature and voltage changes. It's meant for your purpose. Peter Alfke, Xilinx

Reply to
Peter Alfke

Hi

I had downloaded a DDR SDRAM reference design from xilinx for V2P. Actually I have used MIG007 (rev 6) to create the design. This design uses LUT based delay mechanism to align the strobes. The design can be test on Xilinx SL361, ML361, and ML367 boards.

I would like to know whether anyone has tested this reference design on non-Xilinx boards?

Thanks

-- Amy

Reply to
Amy

Peter Alfke schrieb:

I'm interested in time to digital conversion, may the IDELAY used therefore?

Bye Tom

Reply to
Thomas Reinemann

Hmm.. I thought there was reference code.

It's fairly simple - you should be able to find a LUT primitive on the libraries guide, or in unisim.vhd. If you're using synplify, you might be able to use fmaps instead, which give you things to attach tags to, while keeping the logic human-readable.

You'll need appropriate incantations to avoid your synthesiser optimising it away.

For your application, you'll probably also want RLOCs to lock the Luts into relative positions, and you'll probably also want to lock the origin of each macro onto the die.

(Virtex-4 is way better for that kind of technique)

my 2c Jeremy

Reply to
Jeremy Stringer

IDELAY lets you specify an input delay (in 64 increments within a 5 ns window = 75 ps granularity), It generates, but it does not really measure the delay. Changing the delay setting is not instantaneous. I have played around with using multiple different delay driven by a common input signal, and then checking the arrival time. It gets a bit convoluted. But IDELAY is good for aligning signals with known delay offset. There is some pattern sensitivity, which means delaying the clock is more precise than delaying the data. (Sometimes you have a choice...)

Peter Alfke, Xilinx Applications

Reply to
Peter Alfke

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