Hello all,
I am trying to implement a network adapter that sends small packets to and from FPGA boards using VHDL. I want to download this and test it out, but I am getting the following synthesis error when I try to generate the bit file in Xilinx:
Related source file is "usa/delvecch/project1/Packet_Gen.vhd" ERROR:Xst:2108 - Logic for signal is controlled by a clock but does not appear to be a valid sequential description ERROR:Xst:1431 - Failed to synthesize unit .
Here is my code for the packet generation module:
library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all;
entity Packet_Gen is port( clkin: in std_logic; reset: in std_logic; load: in std_logic; fwd: in std_logic; dest_addr: in std_logic_vector (1 downto 0); packet_fwd: in std_logic_vector (5 downto 0); packet_out: out std_logic_vector (5 downto 0)); end Packet_Gen;
architecture behavioral of Packet_Gen is signal load_prev: std_logic := '0';
begin PG_proc: process (clkin, reset) is
begin if (reset = '0') then packet_out