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Re: VHDL Synchronization- two stage FF on all inputs?
rickman wrote:
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Any older ones?  CMOS flip-flops built from transfer gates will not
oscillate.  The only reputable instances I could find showing
oscillation referred to much older families that used cross-coupled
gates.  Note that there are no "Q and Q not" outputs of a CMOS
flip-flop unless "Q not" is generated with an inversion after the
transfer gate latch.  Cross-coupled gate implementations could
oscillate.  You won't find those in an FPGA.

Re: VHDL Synchronization- two stage FF on all inputs?
A simple thought on the topic, as it's often difficult to see the forest
for the trees:


When an asynchronous signal is sampled, there can be timing violations. No
number of chained FFs can give a _deterministic_ result. But they guarantee
that it won't change between clock cycles and will look the same to all
connected inputs, whatever the value.  


For example, a metastable reset could release some blocks one cycle before
others, and the circuit is off to a bad start.        

                    
---------------------------------------        
Posted through http://www.FPGARelated.com

Re: VHDL Synchronization- two stage FF on all inputs?
On 12/16/2014 11:58 AM, GaborSzakacs wrote:
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If you are talking about the circuit shown in your reference it will  
still oscillate the same way as a gate based FF.  Each inverter in the  
loop produces a signal, one is Q the other is Q not whether it is  
labeled as such or not.  Oscillations happen.

--  

Rick

Re: VHDL Synchronization- two stage FF on all inputs?
rickman wrote:
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OK, so clearly you didn't actually read the artical.

1)  Those inverters in a loop are "latches" that work because
there are exactly two inversions forming positive feedback.

2)  There is no Q not as you would have in a cross-coupled gate
flip-flop.  i.e. the middle of each inverter pair is not
accessible.  In fact you could re-draw the schematics showing
the pair as a single non-inverting buffer and it would not
change the way the circuit works.  There is no need for inversion
to hold the current state.

3) Oscillations don't "happen."  The most you'll get is two
transitions when you go into metastability and eventually
resolve to the original state (0 to 0 or 1 to 1).

In any case, this thread is getting too old...

As someone said in another recent thread:

whatever

--  
Gabor

Re: VHDL Synchronization- two stage FF on all inputs?
On 12/17/2014 3:47 PM, GaborSzakacs wrote:
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Yes, two inverters in a loop.  Bistable with delays in each element...  
that part is *exactly* the same as the cross coupled gates and this is  
*exactly* the feature that allows oscillations.


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Whether or not the inverted signal is brought out is irrelevant.  If you  
don't like the name "Q not" tell me what you wish to call it.  Then  
substitute that name in the explanation I gave and it still describes  
the functionality that will allow oscillations.


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Again, you seem to think hiding the details changes operation of the  
circuit.  There is no such thing as a non-inverting primitive element.  
A "non-inverting" buffer is two inverting buffers cascaded, each with  
delay.  To get a non-inverting element requires either common drain or a  
common gate arrangement of the transistors which are not suitable for  
logic elements.


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Yes, the thread is old as are the excuses for not properly analyzing the  
operation of the circuit.

Try putting this in any simulator and testing it.  If you change the  
data input at the right moment so that the first inverter output has  
changed at the moment the feedback gate closes the loop and the input  
gate disconnects the input, you will have two signals of incompatible  
polarity which will chase each other around the loop.  In a simulator  
the oscillations will persist potentially forever.  In the real world  
they will die out... but in an indeterminate time.  Actually the time is  
determinate... if you can nail down all the variables, *but* the result  
relative to the variables such as the exact time of the input transition  
is very chaotic.  In fact, if I can get an approximate model for the  
typical transistor used in modern digital logic I will run a simulation.

If you just treat the circuit as a bunch of logical elements rather than  
electronics I can see where you would not properly understand the  
operation.  You keep trying to explain the circuit with your view of it  
(which I have tried to explain how it is faulty), but you have not  
explained what is faulty about my view of the circuit.

If you don't wish to discuss this further, that's fine.

--  

Rick

Re: VHDL Synchronization- two stage FF on all inputs?

On Wed, 17 Dec 2014, rickman wrote:

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From my understanding, it does not oscillate - it simply tries to resolve  
and the lesser the initial voltage difference between the two nodes of the  
latch, the bigger the time constant. Any big swing to call it  
"oscillation" should put it out of the metastable state already.

Could it be that the master latch does not oscillate, but during the time  
it being metastable (exponentially resolving), the slave (at that time  
transparent) due to indeterminate logic level and noises does the  
observed oscillation? This could be very misleading.

That's for the flip-flop constructed with pass gates, which should be  
close to what is actually used these days (?). I have no direct ASIC  
experience.

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Rick, if you happen to make such simulation, please share the results.

One of the more interesting threads.

Re: VHDL Synchronization- two stage FF on all inputs?
Vladimir Ivanov wrote:
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There are a bunch of simulations in the document.  None of them oscillate.

Bye

Re: VHDL Synchronization- two stage FF on all inputs?
On 15/12/14 23:14, GaborSzakacs wrote:
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Oscillation vs invalid level is dependent on the logic family.
I would go and dig out some 30/40 year old oscillograms, but
they are currently inaccessible.

Re: VHDL Synchronization- two stage FF on all inputs?
Thank you, this has been very helpful for me.  I feel like a small light
bulb turned on in my head, though its fluorescent and it flickers on a off
a bit before staying on :)


I think we can agree that metastability is bad and a dual flip flop on an
input signal can resolve this.  We can add more FF in series to get the
probability of a metastability event down to "zero", but lets say that two
is good enough.  Back to my original question is how would one do this for
a large design with many inputs?


Consider my sample code below, lets say I have a design that has 85 inputs.
 To synchronized everything with dual FF would require 170 internal
signals.  No big deal if you have an large enough FPGA, but is this a
realistic thing to do?   In a CPLD this would take up a lot of resources.


How many out there are actually doing this?  
Is there a better way of doing it?

---------------------------------------------------------------------------------
--  Sample code - Dual FF on all input?
---------------------------------------------------------------------------------
entity BigDesign is
port(
 Clk : in std_logic;
 IN1 : in std_logic;
 .
 .
 .
 .
 .
 IN85 : in std_logic;
 out  : out std_logic
 );
end BigDesign;

archictecture behavioral of BigDesign is

Signal IN1_meta : std_logic;
signal IN1_Sync : std_logic;

Re: VHDL Synchronization- two stage FF on all inputs?
On Fri, 12 Dec 2014 17:00:57 -0600

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Once again, sometimes you would and sometimes you wouldn't.  Let's take
the fairly common case of an 8-bit data bus with an active low latch
signal.  The falling edge of the latch indicates that the data is
valid, and that you should latch it.

In this case, the only thing that actually requires synchronization is
the latch signal itself.  Once you resynchronize it, and see that the
new value of that synced signal is 0 whereas it used to be 1, then you
can latch the 8-bit data presented because you know that it's stable
(by contract) at the time of the falling latch.

Now, the time it takes you to delay may violate that contract; if your
two flip-flops are on a 100 MHz clock that's 20 ns; if you're only
guaranteed 20 ns of data valid then you need to add 1 level of
registers on all that data too.  But that's not there to deal with
metastability, it's just there to try to match your delays up because,
on the clock when you latch the data than you intend to be latched by
the falling-edge detector, the data will be stably 0 or 1 and so
there's no metastability risk.  

--  
Rob Gaddi, Highland Technology -- www.highlandtechnology.com
Email address domain is currently out of order.  See above to fix.

Re: VHDL Synchronization- two stage FF on all inputs?
On 12/12/2014 6:18 PM, Rob Gaddi wrote:
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I will add that you don't need two *additional* FFs for each input.  It  
is not the FF that deals with metastability, it is the slack time in the  
path to the next FF.  So you only need to add one FF per input with no  
logic (or sometimes you can violate that rule if the logic is simple and  
you use a timing constraint to provide guaranteed slack) in the path to  
the next FF.  Really, it is not how much logic there is, the issue is  
slack time to resolve the metastable event before reaching the next FF.  
  So in theory, even a path with no logic can have a bad route with very  
little slack time if the clock is fast enough.

I've never done this, but it would be good practice to use a separate  
timing constraint to assure slack time on the path you are using to  
resolve the metastable events on the input.

--  

Rick

Re: VHDL Synchronization- two stage FF on all inputs?
On Friday, December 12, 2014 6:01:00 PM UTC-5, hvo wrote:
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o
r

Read the last paragraph of my Dec 10 post for the short answer.  Whether a  
design has a large or small number of inputs is not relevant.  What you nee
d to know is the clock that is used to generate those inputs from their ext
ernal source.

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s.

No flip flops are needed if:
- In1...In85 are generated synchronous to Clk
- The setup and hold time requirements of In1...In85 to your design are met
.

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You need to study up on how to perform static timing analysis.  As I mentio
ned in my first post, what you're struggling with has nothing to do with me
tastability.  What it does have to do with is simply timing analysis.  As a
n example, if In1...In85 all are guaranteed to arrive at the input pins bet
ween 1 and 5 ns after the rising edge of a 10 ns clock period Clk input, an
d the setup time for your design requires 3 ns of setup time and 0 ns of ho
ld time, then you have sufficient margin.  If the setup time requirement of
 In43 happens to be 6 ns then you have a 1 ns problem on one input that nee
ds to be fixed.

All of this information comes out of the timing report.  The input to the t
iming report is the routed design and the timing constraints (in the above  
case that In1...In85 all have between 1 and 5 ns of delay).

Kevin Jennings

Re: VHDL Synchronization- two stage FF on all inputs?
On 12/10/2014 7:26 PM, glen herrmannsfeldt wrote:
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???  Not being wrong doesn't sound the same as being right....


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Not sure what that means in the real world.


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It may be right, but is not relevant to the original issue.


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--  

Rick

Re: VHDL Synchronization- two stage FF on all inputs?
On Wed, 10 Dec 2014 14:21:01 -0500, rickman wrote:

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I suspect that the paper (which doesn't sound very thorough) is  
presupposing that you take a design with a given propagation delay, and  
just start turning the frequency down on the clock.

--  

Tim Wescott
Wescott Design Services
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Re: VHDL Synchronization- two stage FF on all inputs?
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(snip on metastability and slack time)

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Much easier than increasing the propagation delay. If your clock is
1MHz, it takes a lot of logic and routing to make a significant fraction
of that in propagation delay.  

-- glen


Re: VHDL Synchronization- two stage FF on all inputs?
On Tuesday, December 9, 2014 7:22:46 PM UTC-5, hvo wrote:
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Actually, it is much more likely that the problem you saw has absolutely no
thing to do with metastability.  What you described and how you fixed it so
unds like either a clock domain crossing or possibly clock skew between the
 part generating the input signal and your internal design clock...in short
 it is a setup/hold time problem.  What you added to fix your design sounds
 like a single flip flop per input signal, then that also suggests the prob
lem is not metastability.  The point here is not to belabor terminology, bu
t to help you understand it.

Any of your inputs that lead through logic that ends in a flip flop (which  
will be every input signal in nearly any design) will have setup and hold t
ime requirements that must be met.  To find out what your requirements are  
review the timing analysis report for your design where the setup and hold  
time requirements for each input will be listed.  Those timing requirements
 are relative to some clock signal in your design.  Do those signals actual
ly get generated in the same clock domain?  If so, is Tco + PCB prop delay  
+ Setup time requirement + Clock Skew less than the clock period?  If those
 signals are not generated in the same clock domain, then ask yourself how  
is that input going to be able to meet the setup and hold time requirements
?  (Hint:  The answer is that it will not).  This is the situation where yo
u are crossing clock domains and the synchronizing flip flop that you added
 is needed.

The setup/hold time requirements will still not be met at the input to that
 flip flop but that is 'OK', since the rest of your design uses the output  
of the flip flop, not the input.  Now that synchronizing flip flop might mi
sbehave (i.e. take a longer than normal time to settle) because the inputs  
did not meet the setup/hold time requirements, so the solution there is to  
add a second flip flop and then the rest of your design uses the output of  
the second flip flop.  The first flip flop 'misbehavior' is what is called  
metastability.  Generally, a two flip flop chain is all that is required to
 cross the clock domain and reduce metastability to an acceptably low numbe
r.

The short answer to your question though is that whenever an input signal d
oes not meet the setup and hold time requirements of your design, you will  
need to synchronize it first before using it elsewhere in your design.

Kevin Jennings

Re: VHDL Synchronization- two stage FF on all inputs?
On Tue, 09 Dec 2014 18:22:41 -0600, hvo wrote:

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By having lots of such inputs -- but see the other, more detailed answers  
for a better idea.

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Any input that is guaranteed to be settled when you clock it in.

--  

Tim Wescott
Wescott Design Services
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Re: VHDL Synchronization- two stage FF on all inputs?
On 2014-12-10 hvo wrote in comp.arch.fpga:
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But why would you want to save a few FFs? Are you running short? Or is
the added delay too much for you? Adding the FFs can also help the tools
place your design more easily.

Okay my current design is in a luxury position. I needed the Xilinx
Zynq for it's dual core processor and a little bit of FPGA. I'm left
with a huge amount of unused FFs even after using triple synchronizers
on all inputs.  

--  
Stef    (remove caps, dashes and .invalid from e-mail address to reply by mail)

Children are like cats, they can tell when you don't like them.  That's
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Re: VHDL Synchronization- two stage FF on all inputs?
On 12/11/2014 6:59 PM, Stef wrote:
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Triple!!!  You are aware that using synchronizers in odd numbers puts  
the metastability back into the circuit, right?


April Fools!  Er, December Fools.

--  

Rick

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