VHDL simulation

I have a schematic of a 4bit adder in my CAD program. It has the ability to create a "VHDL schematic netlist". I've been trying to find a software package that I can use to simulate this schematic. It says "It can be used in conjunction with PLD software from Altera and Xilinx.

Could someone recomend to me the program from Altera or Xilinx? Hopefully there is a free version?

I don't need to simulate my schematic as if it were TTL logic, I just want to make sure it works. I will be expanding it to 32bits and there will be a lot of places for errors!!!

I've atached the VHDL and EDIF files.

Thanks!

LIBRARY IEEE USE IEEE.std_logic_1164.all

ENTITY MULTIPLY IS PORT ( ); END MULTIPLY;

ARCHITECTURE STRUCTURE OF MULTIPLY IS

-- COMPONENTS

COMPONENT TTL__74LS04 PORT ( I_A : IN std_logic; O_A : OUT std_logic; I_B : IN std_logic; O_B : OUT std_logic; I_C : IN std_logic; O_C : OUT std_logic; GND : IN std_logic; O_D : OUT std_logic; I_D : IN std_logic; O_E : OUT std_logic; I_E : IN std_logic; O_F : OUT std_logic; I_F : IN std_logic; VCC : IN std_logic ); END COMPONENT;

COMPONENT TTL__74LS02 PORT ( O_A : OUT std_logic; I0_A : IN std_logic; I1_A : IN std_logic; O_B : OUT std_logic; I0_B : IN std_logic; I1_B : IN std_logic; GND : IN std_logic; I0_C : IN std_logic; I1_C : IN std_logic; O_C : OUT std_logic; I0_D : IN std_logic; I1_D : IN std_logic; O_D : OUT std_logic; VCC : IN std_logic ); END COMPONENT;

COMPONENT TTL__74LS00 PORT ( I0_A : IN std_logic; I1_A : IN std_logic; O_A : OUT std_logic; I0_B : IN std_logic; I1_B : IN std_logic; O_B : OUT std_logic; GND : IN std_logic; O_C : OUT std_logic; I0_C : IN std_logic; I1_C : IN std_logic; O_D : OUT std_logic; I0_D : IN std_logic; I1_D : IN std_logic; VCC : IN std_logic ); END COMPONENT;

COMPONENT TTL__74LS08 PORT ( I0_A : IN std_logic; I1_A : IN std_logic; O_A : OUT std_logic; I0_B : IN std_logic; I1_B : IN std_logic; O_B : OUT std_logic; GND : IN std_logic; O_C : OUT std_logic; I0_C : IN std_logic; I1_C : IN std_logic; O_D : OUT std_logic; I0_D : IN std_logic; I1_D : IN std_logic; VCC : IN std_logic ); END COMPONENT;

COMPONENT TTL__74LS11 PORT ( I0_A : IN std_logic; I1_A : IN std_logic; I0_B : IN std_logic; I1_B : IN std_logic; I2_B : IN std_logic; O_B : OUT std_logic; GND : IN std_logic; O_C : OUT std_logic; I0_C : IN std_logic; I1_C : IN std_logic; I2_C : IN std_logic; O_A : OUT std_logic; I2_A : IN std_logic; VCC : IN std_logic ); END COMPONENT;

COMPONENT TTL__74LS21 PORT ( I0_A : IN std_logic; I1_A : IN std_logic; I2_A : IN std_logic; I3_A : IN std_logic; O_A : OUT std_logic; GND : IN std_logic; O_B : OUT std_logic; I0_B : IN std_logic; I1_B : IN std_logic; I2_B : IN std_logic; I3_B : IN std_logic; VCC : IN std_logic ); END COMPONENT;

COMPONENT TTL__7425 PORT ( I0_A : IN std_logic; I1_A : IN std_logic; G_A : IN std_logic; I2_A : IN std_logic; I3_A : IN std_logic; O_A : OUT std_logic; GND : IN std_logic; O_B : OUT std_logic; I0_B : IN std_logic; I1_B : IN std_logic; G_B : IN std_logic; I2_B : IN std_logic; I3_B : IN std_logic; VCC : IN std_logic ); END COMPONENT;

COMPONENT TTL__74LS27 PORT ( I0_A : IN std_logic; I1_A : IN std_logic; I0_B : IN std_logic; I1_B : IN std_logic; I2_B : IN std_logic; O_B : OUT std_logic; GND : IN std_logic; O_C : OUT std_logic; I0_C : IN std_logic; I1_C : IN std_logic; I2_C : IN std_logic; O_A : OUT std_logic; I2_A : IN std_logic; VCC : IN std_logic ); END COMPONENT;

COMPONENT TTL__74LS86 PORT ( I0_A : IN std_logic; I1_A : IN std_logic; O_A : OUT std_logic; I0_B : IN std_logic; I1_B : IN std_logic; O_B : OUT std_logic; GND : IN std_logic; O_C : OUT std_logic; I0_C : IN std_logic; I1_C : IN std_logic; O_D : OUT std_logic; I0_D : IN std_logic; I1_D : IN std_logic; VCC : IN std_logic ); END COMPONENT;

-- SIGNALS

SIGNAL A0_1 : std_logic; SIGNAL A0_NAND_B0_1 : std_logic; SIGNAL A0_NOR_B0_1 : std_logic; SIGNAL A1_1 : std_logic; SIGNAL A1_NAND_B1_1 : std_logic; SIGNAL A1_NOR_B1_1 : std_logic; SIGNAL A2_1 : std_logic; SIGNAL A2_NAND_B2_1 : std_logic; SIGNAL A2_NOR_B2_1 : std_logic; SIGNAL A3_1 : std_logic; SIGNAL A3_NAND_B3_1 : std_logic; SIGNAL A3_NOR_B3_1 : std_logic; SIGNAL B0_1 : std_logic; SIGNAL B1_1 : std_logic; SIGNAL B2_1 : std_logic; SIGNAL B3_1 : std_logic; SIGNAL \C\\A\\R\\R\\Y\\_\\I\\N\\_1\ : std_logic; SIGNAL CARRY_IN_1 : std_logic; SIGNAL GND : std_logic; SIGNAL S0_1 : std_logic; SIGNAL S1_1 : std_logic; SIGNAL S2_1 : std_logic; SIGNAL S3_1 : std_logic; SIGNAL VCC : std_logic; SIGNAL NET10_1 : std_logic; SIGNAL NET11_1 : std_logic; SIGNAL NET12_1 : std_logic; SIGNAL NET13_1 : std_logic; SIGNAL NET14_1 : std_logic; SIGNAL NET15_1 : std_logic; SIGNAL NET16_1 : std_logic; SIGNAL NET17_1 : std_logic; SIGNAL NET18_1 : std_logic; SIGNAL NET1_1 : std_logic; SIGNAL NET2_1 : std_logic; SIGNAL NET3_1 : std_logic; SIGNAL NET4_1 : std_logic; SIGNAL NET5_1 : std_logic; SIGNAL NET6_1 : std_logic; SIGNAL NET7_1 : std_logic; SIGNAL NET8_1 : std_logic; SIGNAL NET9_1 : std_logic;

-- GATE INSTANCES

BEGIN

U1 : TTL__74LS04 PORT MAP ( I_A => CARRY_IN_1, O_A => \C\\A\\R\\R\\Y\\_\\I\\N\\_1\, I_B => A3_NOR_B3_1, O_B => NET15_1, I_C => A2_NOR_B2_1, O_C => NET12_1, GND => GND, O_D => NET10_1, I_D => A1_NOR_B1_1, O_E => NET9_1, I_E => A0_NOR_B0_1, O_F => NET1_1, I_F => \C\\A\\R\\R\\Y\\_\\I\\N\\_1\, VCC => VCC );

U2 : TTL__74LS02 PORT MAP ( O_A => A0_NOR_B0_1, I0_A => A0_1, I1_A => B0_1, O_B => A1_NOR_B1_1, I0_B => A1_1, I1_B => B1_1, GND => GND, I0_C => A2_1, I1_C => B2_1, O_C => A2_NOR_B2_1, I0_D => A3_1, I1_D => B3_1, O_D => A3_NOR_B3_1, VCC => VCC );

U3 : TTL__74LS00 PORT MAP ( I0_A => A0_1, I1_A => B0_1, O_A => A0_NAND_B0_1, I0_B => A1_1, I1_B => B1_1, O_B => A1_NAND_B1_1, GND => GND, O_C => A2_NAND_B2_1, I0_C => A2_1, I1_C => B2_1, O_D => A3_NAND_B3_1, I0_D => A3_1, I1_D => B3_1, VCC => VCC );

U4 : TTL__74LS08 PORT MAP ( I0_A => A1_NOR_B1_1, I1_A => A2_NAND_B2_1, O_A => NET18_1, I0_B => NET15_1, I1_B => A3_NAND_B3_1, O_B => NET3_1, GND => GND, O_C => NET14_1, I0_C => A0_NOR_B0_1, I1_C => A0_NAND_B0_1, O_D => NET5_1, I0_D => NET12_1, I1_D => A2_NAND_B2_1, VCC => VCC );

U5 : TTL__74LS11 PORT MAP ( I0_A => A0_NOR_B0_1, I1_A => A1_NAND_B1_1, I0_B => \C\\A\\R\\R\\Y\\_\\I\\N\\_1\, I1_B => A0_NAND_B0_1, I2_B => A1_NAND_B1_1, O_B => NET13_1, GND => GND, O_C => OPEN, I0_C => OPEN, I1_C => OPEN, I2_C => OPEN, O_A => NET17_1, I2_A => A2_NAND_B2_1, VCC => VCC );

U6 : TTL__74LS21 PORT MAP ( I0_A => \C\\A\\R\\R\\Y\\_\\I\\N\\_1\, I1_A => A0_NAND_B0_1, I2_A => A1_NAND_B1_1, I3_A => A2_NAND_B2_1, O_A => NET16_1, GND => GND, O_B => OPEN, I0_B => OPEN, I1_B => OPEN, I2_B => OPEN, I3_B => OPEN, VCC => VCC );

U7 : TTL__7425 PORT MAP ( I0_A => A2_NOR_B2_1, I1_A => NET18_1, G_A => OPEN, I2_A => NET17_1, I3_A => NET16_1, O_A => NET2_1, GND => GND, O_B => OPEN, I0_B => OPEN, I1_B => OPEN, G_B => OPEN, I2_B => OPEN, I3_B => OPEN, VCC => VCC );

U8 : TTL__74LS27 PORT MAP ( I0_A => A1_NOR_B1_1, I1_A => NET14_1, I0_B => OPEN, I1_B => OPEN, I2_B => OPEN, O_B => OPEN, GND => GND, O_C => OPEN, I0_C => OPEN, I1_C => OPEN, I2_C => OPEN, O_A => NET4_1, I2_A => NET13_1, VCC => VCC );

U9 : TTL__74LS08 PORT MAP ( I0_A => \C\\A\\R\\R\\Y\\_\\I\\N\\_1\, I1_A => A0_NAND_B0_1, O_A => NET11_1, I0_B => NET10_1, I1_B => A1_NAND_B1_1, O_B => NET7_1, GND => GND, O_C => NET8_1, I0_C => NET9_1, I1_C => A0_NAND_B0_1, O_D => OPEN, I0_D => OPEN, I1_D => OPEN, VCC => VCC );

U10 : TTL__74LS02 PORT MAP ( O_A => NET6_1, I0_A => A0_NOR_B0_1, I1_A => NET11_1, O_B => OPEN, I0_B => OPEN, I1_B => OPEN, GND => GND, I0_C => OPEN, I1_C => OPEN, O_C => OPEN, I0_D => OPEN, I1_D => OPEN, O_D => OPEN, VCC => VCC );

U11 : TTL__74LS86 PORT MAP ( I0_A => NET1_1, I1_A => NET8_1, O_A => S0_1, I0_B => NET7_1, I1_B => NET6_1, O_B => S1_1, GND => GND, O_C => S2_1, I0_C => NET5_1, I1_C => NET4_1, O_D => S3_1, I0_D => NET3_1, I1_D => NET2_1, VCC => VCC );

END STRUCTURE;

And here is the EDIF:

(edif MULTIPLY (edifVersion 2 0 0) (edifLevel 0) (keywordMap (keywordLevel 0)) (status (written (timeStamp 2006 02 16 17 37 48) (program "SchEdit.exe") (comment "Original data from Qcad/Schematics")) (comment "MULTIPLY") (comment "Thursday, February 16, 2006") (comment "1") (comment "1") (comment "Microcad") (comment "1-416-783-8886") (comment "") (comment "") (comment "")) (external QCAD_LIB (edifLevel 0) (technology (numberDefinition (scale 1 1 (unit distance)))) (cell &74LS04 (cellType generic) (comment "From QCAD library TTL") (view NetlistView (viewType netlist) (interface (port I_A (direction INPUT)) (port O_A (direction OUTPUT)) (port I_B (direction INPUT)) (port O_B (direction OUTPUT)) (port I_C (direction INPUT)) (port O_C (direction OUTPUT)) (port GND (direction INPUT)) (port O_D (direction OUTPUT)) (port I_D (direction INPUT)) (port O_E (direction OUTPUT)) (port I_E (direction INPUT)) (port O_F (direction OUTPUT)) (port I_F (direction INPUT)) (port VCC (direction INPUT))))) (cell &74LS02 (cellType generic) (comment "From QCAD library TTL") (view NetlistView (viewType netlist) (interface (port O_A (direction OUTPUT)) (port I0_A (direction INPUT)) (port I1_A (direction INPUT)) (port O_B (direction OUTPUT)) (port I0_B (direction INPUT)) (port I1_B (direction INPUT)) (port GND (direction INPUT)) (port I0_C (direction INPUT)) (port I1_C (direction INPUT)) (port O_C (direction OUTPUT)) (port I0_D (direction INPUT)) (port I1_D (direction INPUT)) (port O_D (direction OUTPUT)) (port VCC (direction INPUT))))) (cell &74LS00 (cellType generic) (comment "From QCAD library TTL") (view NetlistView (viewType netlist) (interface (port I0_A (direction INPUT)) (port I1_A (direction INPUT)) (port O_A (direction OUTPUT)) (port I0_B (direction INPUT)) (port I1_B (direction INPUT)) (port O_B (direction OUTPUT)) (port GND (direction INPUT)) (port O_C (direction OUTPUT)) (port I0_C (direction INPUT)) (port I1_C (direction INPUT)) (port O_D (direction OUTPUT)) (port I0_D (direction INPUT)) (port I1_D (direction INPUT)) (port VCC (direction INPUT))))) (cell &74LS08 (cellType generic) (comment "From QCAD library TTL") (view NetlistView (viewType netlist) (interface (port I0_A (direction INPUT)) (port I1_A (direction INPUT)) (port O_A (direction OUTPUT)) (port I0_B (direction INPUT)) (port I1_B (direction INPUT)) (port O_B (direction OUTPUT)) (port GND (direction INPUT)) (port O_C (direction OUTPUT)) (port I0_C (direction INPUT)) (port I1_C (direction INPUT)) (port O_D (direction OUTPUT)) (port I0_D (direction INPUT)) (port I1_D (direction INPUT)) (port VCC (direction INPUT))))) (cell &74LS11 (cellType generic) (comment "From QCAD library TTL") (view NetlistView (viewType netlist) (interface (port I0_A (direction INPUT)) (port I1_A (direction INPUT)) (port I0_B (direction INPUT)) (port I1_B (direction INPUT)) (port I2_B (direction INPUT)) (port O_B (direction OUTPUT)) (port GND (direction INPUT)) (port O_C (direction OUTPUT)) (port I0_C (direction INPUT)) (port I1_C (direction INPUT)) (port I2_C (direction INPUT)) (port O_A (direction OUTPUT)) (port I2_A (direction INPUT)) (port VCC (direction INPUT))))) (cell &74LS21 (cellType generic) (comment "From QCAD library TTL") (view NetlistView (viewType netlist) (interface (port I0_A (direction INPUT)) (port I1_A (direction INPUT)) (port I2_A (direction INPUT)) (port I3_A (direction INPUT)) (port O_A (direction OUTPUT)) (port GND (direction INPUT)) (port O_B (direction OUTPUT)) (port I0_B (direction INPUT)) (port I1_B (direction INPUT)) (port I2_B (direction INPUT)) (port I3_B (direction INPUT)) (port VCC (direction INPUT))))) (cell &7425 (cellType generic) (comment "From QCAD library TTL") (view NetlistView (viewType netlist) (interface (port I0_A (direction INPUT)) (port I1_A (direction INPUT)) (port G_A (direction INPUT)) (port I2_A (direction INPUT)) (port I3_A (direction INPUT)) (port O_A (direction OUTPUT)) (port GND (direction INPUT)) (port O_B (direction OUTPUT)) (port I0_B (direction INPUT)) (port I1_B (direction INPUT)) (port G_B (direction INPUT)) (port I2_B (direction INPUT)) (port I3_B (direction INPUT)) (port VCC (direction INPUT))))) (cell &74LS27 (cellType generic) (comment "From QCAD library TTL") (view NetlistView (viewType netlist) (interface (port I0_A (direction INPUT)) (port I1_A (direction INPUT)) (port I0_B (direction INPUT)) (port I1_B (direction INPUT)) (port I2_B (direction INPUT)) (port O_B (direction OUTPUT)) (port GND (direction INPUT)) (port O_C (direction OUTPUT)) (port I0_C (direction INPUT)) (port I1_C (direction INPUT)) (port I2_C (direction INPUT)) (port O_A (direction OUTPUT)) (port I2_A (direction INPUT)) (port VCC (direction INPUT))))) (cell &74LS86 (cellType generic) (comment "From QCAD library TTL") (view NetlistView (viewType netlist) (interface (port I0_A (direction INPUT)) (port I1_A (direction INPUT)) (port O_A (direction OUTPUT)) (port I0_B (direction INPUT)) (port I1_B (direction INPUT)) (port O_B (direction OUTPUT)) (port GND (direction INPUT)) (port O_C (direction OUTPUT)) (port I0_C (direction INPUT)) (port I1_C (direction INPUT)) (port O_D (direction OUTPUT)) (port I0_D (direction INPUT)) (port I1_D (direction INPUT)) (port VCC (direction INPUT)))))) (library MAIN_LIB (edifLevel 0) (technology (numberDefinition (scale 1 1 (unit distance)))) (cell MULTIPLY (cellType generic) (view NetlistView (viewType netlist) (interface) (contents (instance U1 (viewRef NetlistView (cellRef &74LS04 (libraryRef QCAD_LIB)))) (instance U2 (viewRef NetlistView (cellRef &74LS02 (libraryRef QCAD_LIB)))) (instance U3 (viewRef NetlistView (cellRef &74LS00 (libraryRef QCAD_LIB)))) (instance U4 (viewRef NetlistView (cellRef &74LS08 (libraryRef QCAD_LIB)))) (instance U5 (viewRef NetlistView (cellRef &74LS11 (libraryRef QCAD_LIB)))) (instance U6 (viewRef NetlistView (cellRef &74LS21 (libraryRef QCAD_LIB)))) (instance U7 (viewRef NetlistView (cellRef &7425 (libraryRef QCAD_LIB)))) (instance U8 (viewRef NetlistView (cellRef &74LS27 (libraryRef QCAD_LIB)))) (instance U9 (viewRef NetlistView (cellRef &74LS08 (libraryRef QCAD_LIB)))) (instance U10 (viewRef NetlistView (cellRef &74LS02 (libraryRef QCAD_LIB)))) (instance U11 (viewRef NetlistView (cellRef &74LS86 (libraryRef QCAD_LIB)))) (net A0_1 (joined (portRef I0_A (instanceRef U2)) (portRef I0_A (instanceRef U3)))) (net A0_NAND_B0_1 (joined (portRef O_A (instanceRef U3)) (portRef I1_C (instanceRef U4)) (portRef I1_B (instanceRef U5)) (portRef I1_A (instanceRef U6)) (portRef I1_C (instanceRef U9)) (portRef I1_A (instanceRef U9)))) (net A0_NOR_B0_1 (joined (portRef I_E (instanceRef U1)) (portRef O_A (instanceRef U2)) (portRef I0_C (instanceRef U4)) (portRef I0_A (instanceRef U5)) (portRef I0_A (instanceRef U10)))) (net A1_1 (joined (portRef I0_B (instanceRef U2)) (portRef I0_B (instanceRef U3)))) (net A1_NAND_B1_1 (joined (portRef O_B (instanceRef U3)) (portRef I1_A (instanceRef U5)) (portRef I2_B (instanceRef U5)) (portRef I2_A (instanceRef U6)) (portRef I1_B (instanceRef U9)))) (net A1_NOR_B1_1 (joined (portRef I_D (instanceRef U1)) (portRef O_B (instanceRef U2)) (portRef I0_A (instanceRef U4)) (portRef I0_A (instanceRef U8)))) (net A2_1 (joined (portRef I0_C (instanceRef U2)) (portRef I0_C (instanceRef U3)))) (net A2_NAND_B2_1 (joined (portRef O_C (instanceRef U3)) (portRef I1_D (instanceRef U4)) (portRef I1_A (instanceRef U4)) (portRef I2_A (instanceRef U5)) (portRef I3_A (instanceRef U6)))) (net A2_NOR_B2_1 (joined (portRef I_C (instanceRef U1)) (portRef O_C (instanceRef U2)) (portRef I0_A (instanceRef U7)))) (net A3_1 (joined (portRef I0_D (instanceRef U2)) (portRef I0_D (instanceRef U3)))) (net A3_NAND_B3_1 (joined (portRef O_D (instanceRef U3)) (portRef I1_B (instanceRef U4)))) (net A3_NOR_B3_1 (joined (portRef I_B (instanceRef U1)) (portRef O_D (instanceRef U2)))) (net B0_1 (joined (portRef I1_A (instanceRef U2)) (portRef I1_A (instanceRef U3)))) (net B1_1 (joined (portRef I1_B (instanceRef U2)) (portRef I1_B (instanceRef U3)))) (net B2_1 (joined (portRef I1_C (instanceRef U2)) (portRef I1_C (instanceRef U3)))) (net B3_1 (joined (portRef I1_D (instanceRef U2)) (portRef I1_D (instanceRef U3)))) (net CBARABARRBARRBARYBAR_BARIBARNBAR_1 (joined (portRef I_F (instanceRef U1)) (portRef O_A (instanceRef U1)) (portRef I0_B (instanceRef U5)) (portRef I0_A (instanceRef U6)) (portRef I0_A (instanceRef U9)))) (net CARRY_IN_1 (joined (portRef I_A (instanceRef U1)))) (net GND (joined (portRef GND (instanceRef U1)) (portRef GND (instanceRef U2)) (portRef GND (instanceRef U3)) (portRef GND (instanceRef U4)) (portRef GND (instanceRef U5)) (portRef GND (instanceRef U6)) (portRef GND (instanceRef U7)) (portRef GND (instanceRef U8)) (portRef GND (instanceRef U9)) (portRef GND (instanceRef U10)) (portRef GND (instanceRef U11)))) (net S0_1 (joined (portRef O_A (instanceRef U11)))) (net S1_1 (joined (portRef O_B (instanceRef U11)))) (net S2_1 (joined (portRef O_C (instanceRef U11)))) (net S3_1 (joined (portRef O_D (instanceRef U11)))) (net VCC (joined (portRef VCC (instanceRef U1)) (portRef VCC (instanceRef U2)) (portRef VCC (instanceRef U3)) (portRef VCC (instanceRef U4)) (portRef VCC (instanceRef U5)) (portRef VCC (instanceRef U6)) (portRef VCC (instanceRef U7)) (portRef VCC (instanceRef U8)) (portRef VCC (instanceRef U9)) (portRef VCC (instanceRef U10)) (portRef VCC (instanceRef U11)))) (net NET10_1 (joined (portRef O_D (instanceRef U1)) (portRef I0_B (instanceRef U9)))) (net NET11_1 (joined (portRef O_A (instanceRef U9)) (portRef I1_A (instanceRef U10)))) (net NET12_1 (joined (portRef O_C (instanceRef U1)) (portRef I0_D (instanceRef U4)))) (net NET13_1 (joined (portRef O_B (instanceRef U5)) (portRef I2_A (instanceRef U8)))) (net NET14_1 (joined (portRef O_C (instanceRef U4)) (portRef I1_A (instanceRef U8)))) (net NET15_1 (joined (portRef O_B (instanceRef U1)) (portRef I0_B (instanceRef U4)))) (net NET16_1 (joined (portRef O_A (instanceRef U6)) (portRef I3_A (instanceRef U7)))) (net NET17_1 (joined (portRef O_A (instanceRef U5)) (portRef I2_A (instanceRef U7)))) (net NET18_1 (joined (portRef O_A (instanceRef U4)) (portRef I1_A (instanceRef U7)))) (net NET1_1 (joined (portRef O_F (instanceRef U1)) (portRef I0_A (instanceRef U11)))) (net NET2_1 (joined (portRef O_A (instanceRef U7)) (portRef I1_D (instanceRef U11)))) (net NET3_1 (joined (portRef O_B (instanceRef U4)) (portRef I0_D (instanceRef U11)))) (net NET4_1 (joined (portRef O_A (instanceRef U8)) (portRef I1_C (instanceRef U11)))) (net NET5_1 (joined (portRef O_D (instanceRef U4)) (portRef I0_C (instanceRef U11)))) (net NET6_1 (joined (portRef O_A (instanceRef U10)) (portRef I1_B (instanceRef U11)))) (net NET7_1 (joined (portRef O_B (instanceRef U9)) (portRef I0_B (instanceRef U11)))) (net NET8_1 (joined (portRef O_C (instanceRef U9)) (portRef I1_A (instanceRef U11)))) (net NET9_1 (joined (portRef O_E (instanceRef U1)) (portRef I0_C (instanceRef U9)))))))) (design MULTIPLY (cellRef MULTIPLY (libraryRef MAIN_LIB))))

Reply to
logjam
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Hi,

You should be able to use Altera's Quartus II for carrying out this simulation. There is a free web edition of Quartus II at

formatting link

I do know that Quartus II accepts edif as input. But you would have to specify how the gates in your edif map to Quartus II logic functions. For that I think you'll need to create a library mapping file (.lmf). Install Quartus II and then look for instructions on how to do this in 'Help-Index'. For some CAD tools there are already existing .lmf files that specify the mapping to Quartus II logic functions but I don't know if one exists corresponding to the CAD tool that generated your edif.

Of course you can also try creating a schematic for your adder design using the Quartus II schematic editor itself and perhaps that may be easier than trying to use your edif file.

Good luck!

Reply to
Shyam

I think the ultimate thing to do would be making my CAD design directly responsible for the input, so that I can not only vaidate the design but the connections in my schematic. Creating a PCB that doesn't work is one thing, soldering around a hundred gates to it is another! :)

Thanks. I'm downloading it right now, but for some reason the connection reset at 166MB. :(

Reply to
logjam

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