VHDL or Verilog?

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I've been given conflicting device on which language to use.  There
are people I would consider to be expert professionals who tell me
to use VHDL, and others who tell me Verilog.  Most everybody tells
me that if I use VHDL there's less chance for error, but that it
does take more effort to learn.

Any thoughts?

Thank you,
Rick C. Hodgin

Re: VHDL or Verilog?
Rick C. Hodgin wrote on 6/21/2017 8:08 AM:
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I don't recommend one over the other.  It's like asking if steak is "better"  
than Sea Bass.  It depends more on the user than the language.

Verilog has a lot in common with C.  It is more brief to type than VHDL, it  
allows some things to be implied through defaults rather than specified  
explicitly and can be much faster to come up to speed with.  VHDL is much  
more verbose, requires *everything* to be indicated explicitly and can be  
hard to get up to speed with a longer learning curve.

When people talk about "less chance for error" they are referring to the  
strong typing and requirement that everything be explicit.  In Verilog you  
can write code that uses the defaults for type conversions and even things  
like word size adjustments.  So if you aren't familiar with all these  
defaults it may not do what you were hoping for.  In VHDL you don't get to  
take the shortcuts and *must* convert types and adjust all operands and  
results to match.  Otherwise you get error messages that don't always tell  
you what you did wrong.

Personally I find VHDL to be ok, but that is mostly because I've used it for  
some 20 years.  The only thing holding me back from working in Verilog is no  
one can recommend a good Verilog book that covers all the pitfalls.  I've  
been told many times that a good Verilog book has yet to be written.

If you want to learn both (what I actually recommend) I suggest you learn  
VHDL first, get good enough at it that you don't swear every time you have  
to type convert an integer, and only *then* learn Verilog.  Then you will  
have given VHDL a decent chance and you can make your own decision whether  
Verilog is your preference.  I'm pretty sure once you learn Verilog you will  
find learning VHDL to be very annoying.

--  

Rick C

Re: VHDL or Verilog?
On Wednesday, June 21, 2017 at 11:20:04 AM UTC-4, rickman wrote:
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I've had difficulty with the mechanics of Verilog.  I have been able
to go through examples on EDA Playground, for example, but there are
a handful of things I don't yet understand, and they are hindering
me from being able to express ideas into this hardware source code.

I have contacted a local group here in Indianapolis, IN, and they
have some members with hardware skills.  I think they'll be able
to help me.  One of the members there suggested VHDL well ahead of
Verilog.  But for now, I'm going to switch to Arduino and at least
get my prototypes working, even if they're limited, while I spend
my evenings and weekends trying to get the same logic encoded in
my FPGA.

I appreciate your response.  Thank you, Rick C.

Thank you,
Rick C. Hodgin

Re: VHDL or Verilog?
On 21/06/17 17:20, rickman wrote:
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Have you any experience with hardware design languages other than "the  
big two" ?  There are many other possibilities, such as SystemC,  
SystemVerilog, MyHDL, Lava, etc.  I used Confluence for a couple of  
designs, many years ago - it is a functional programming HDL language.  
I found it good for making flexible designs with clean synchronous  
logic, using a fraction of the code needed in Verilog or VHDL for the  
same job.


Re: VHDL or Verilog?
Rick,
Most of the hard things related to conversions and types are summarized in:
http://synthworks.com/papers/vhdl_math_tricks_mapld_2003.pdf

Cheers,
Jim

Re: VHDL or Verilog?
Jim Lewis wrote:
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Thanks, Jim.  I'll check it out.

Thank you,
Rick C. Hodgin

Re: VHDL or Verilog?
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My thought is that you should start with vhdl and ghdl for simulation and g
tkwave for viewing. Or just use Vivado web edition if you want to do things
 in a gui. It is not that much of a learning curve with all the example cod
e available on the net. Most of the tricky things with vhdl and types has a
lready been asked at least once, so google will find solutions to just abou
t any problem you may have in the beginning. It is always possible to go to
 verilog later if you find that vhdl is not for you. With the good mixed la
nguage support in vivado, you would not waste much of your time learning ei
ther. But I never cared to move to verilog so what do I know. (I do transla
te verilog code to vhdl with icarus or by hand so it is not that I haven't  
been exposed to verilog)

--  
Svenn

Re: VHDL or Verilog?
Den onsdag den 21. juni 2017 kl. 14.08.53 UTC+2 skrev Rick C. Hodgin:
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don't you already have enough arguments over religion? ;)




Re: VHDL or Verilog?
snipped-for-privacy@gmail.com wrote on 6/21/2017 5:05 PM:
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I feel that is uncalled for.  When he comes here proselytizing then respond  
about that (or better ignore him).  But when he comes here like the rest of  
us asking for technical help, why pick on him?

--  

Rick C

Re: VHDL or Verilog?
On Wednesday, June 21, 2017 at 5:17:24 PM UTC-4, rickman wrote:
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It's okay.  I thought it was very funny actually.  I couldn't
respond more timely though because I was at a stop light when
I read it. :-)

Thank you,
Rick C. Hodgin

Re: VHDL or Verilog?
Rick C. Hodgin wrote on 6/21/2017 5:28 PM:
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Actually I guess it was rather a joke instead of an insult.  I didn't pick  
up on that.  VHDL vs. Verilog can very much be a religious war.

Sorry Lasse.

--  

Rick C

Re: VHDL or Verilog?
Den onsdag den 21. juni 2017 kl. 23.17.24 UTC+2 skrev rickman:
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if you think is was picking on him that's on you, it was meant as a  
tongue-in-cheeck comment that asking whether you should use verilog or vhdl
is probably going to end like asking what religion is best catholic or protestant. Everyone has a set opinion and soon someone will say you shouldn't
be either and be atheist instead  





Re: VHDL or Verilog?
On Wednesday, June 21, 2017 at 5:42:40 PM UTC-4, snipped-for-privacy@gmail.com wrote:
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Just so everybody's clear also ... I enjoy working with people, and
sharing in our technical expertise.  My posts about salvation and
forgiveness of sin are given because of what's happened in my life.

I'm currently part of a group of people who are from all backgrounds
and interests, with some of them overlapping into the same hardware
and software areas I'm interested in.

As such, it's a very powerful and diverse group of people.  It's the
thing I enjoy ... helping, sharing, expressing, in these areas.  We
are together a more diverse and capable group than we are in iso-
lation.

Thank you,
Rick C. Hodgin

Re: VHDL or Verilog?
On Wednesday, June 21, 2017 at 5:05:50 PM UTC-4, snipped-for-privacy@gmail.com wrote:
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LOL!  I didn't know.  I plea ignorance.

Thank you,
Rick C. Hodgin

Re: VHDL or Verilog?
Rick C. Hodgin wrote:
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Here's an article on that:

https://www.nandland.com/articles/vhdl-or-verilog-for-fpga-asic.html

Re: VHDL or Verilog?
On 21/06/17 14:08, Rick C. Hodgin wrote:
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Have you considered other possibilities?  VHDL and Verilog are the two
main HDL languages, but they are far from the only choices.  There are
many others, most of which give different ways to express the logic that
at least some people consider clearer, less error-prone, or more
productive.  Usually these other tools include different ways to test or
simulate the logic, and generate VHDL and/or Verilog output for
synthesis with FPGA tools.

Note that it is quite a while since I have done any FPGA designs, so my
comments here are based on things I did many years ago, or things I have
read about and learned about but not used in practice.  So if anyone
else has direct experience here, their comments would be valuable.  But
certainly if I were to start working on a new FPGA project, I would look
much wider than Verilog or VHDL before deciding on the tools for the job.

An obvious step up from Verilog is SystemVerilog.  It gives a bit more
structure to interfaces, has a few more types, and has different
"always" blocks that reduce the risk of accidentally generating the
wrong type of logic.  It also has many new non-synthesizable features
for making better simulation testbenches.

Handel-C is an HDL that is a superset of C.  It adds features such as
parallel and sequential blocks, channels for communication between
parallel threads, and HDL concepts such as reset, clocks, etc.

MyHDL is a popular Python-based HDL.  Since it is Python, you have a lot
of freedom and flexibility that you might not get in a lower level HDL.
 It also means that your main testbench code can also be written
directly in Python.


Personally, I used Confluence a long time ago.  This was a functional
programming language HDL.  However, the tool was very much a one-man
project, and when he decided to move on to other things, the project
disappeared - there was never a serious community around it.  But I
found the language let me write much smaller and simpler code, with
fewer problems and shorter test/debug cycles, compared to Verilog.

A big question in this is what sort of designs do you want to make?  One
concept that I like is higher level generators.  For example, consider
making peripherals that are memory mapped on a bus.  Your peripherals
will have some registers that can be read or written from the bus, and
logic to actually /do/ something with the register values (such as a
timer, a UART interface, or whatever).

The bus interface part has a similar structure - you have a list of
registers, information about their sizes, their offsets from the base
address, their read/write capabilities.  You have an address decoder for
the bus, and a bus slave interface that depends on the bus protocol.

You can write such a bus interface in straight Verilog or VHDL.  And
once you have made an interface component for a UART, you can use it
repeatedly for as many UARTs as you want.  But when you want to make the
interface for a timer peripheral, it is copy-and-paste and then you
modify it for the new peripheral.  And so on.  VHDL generics might allow
you a little more re-usability, but my understanding is that the
implementation of them in existing tools is very limited.

But in a higher level HDL, you can write a bus interface generator - a
function or component that takes a list of registers and their details,
and generates an instance of an interface.  So once that generator is
written, you can use it for all your different peripherals.




Re: VHDL or Verilog?
On Thursday, June 22, 2017 at 5:13:02 AM UTC-4, David Brown wrote:
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Thank you for your guidance, David.  Your input is appreciated.

Thank you,
Rick C. Hodgin

Re: VHDL or Verilog?
On 06/22/2017 02:12 AM, David Brown wrote:

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That's actually one of the features going into VHDL-2017, is the concept  
of higher level interfaces.  So you'll be able to bring in an AXI  
package, say that an entity has a AXI interface port, and control the  
bus logic with a couple functions from that package without having to  
cut and paste all that boilerplate.

--  
Rob Gaddi, Highland Technology -- www.highlandtechnology.com
Email address domain is currently out of order.  See above to fix.

Re: VHDL or Verilog?
On Thursday, June 22, 2017 at 5:13:02 AM UTC-4, David Brown wrote:
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To provide a little more detail, I know I've told you before that
I am going to author the Logician tool, which will allow a Blender
nodes-like ability to manipulate objects graphically, and to move
them in 3D space using OpenGL.

-----
I am a very visual person, and I have a hard time reading, and
despite my profession, that actually includes software code as
well.  I prefer to draw things on white boards, on paper, to
have symbols used instead of words for things, etc.  Also,
you've commented before on my unusual spacing in source files,
but I do that because another part of my brain is responsible
for organizing things geometrically, which relieves pressure on
my reading centers, making it easier for me to read.

So, my goals are to learn VHDL or Verilog, and then author the
Logician tool, and then have it translate the visual definition
of that tool into the VHDL or Verilog syntax language for use in
traditional tools.  I do not plan to remain in VHDL or Verilog
for very long.

And for my immediate need, I'm getting conflicting guidance from
the group I've recently become involved with, and I just wanted
some advice from the FPGA group here.  For the time being, I'll
be using Arduino to get my product working while I continue to
devote time to learning my Altera or Lattice FPGA toolkits in
the evenings and weekends.

-----
To all:  I could use some assistance in working with Altera's
         Quartus on a Cyclone V GX Starter Kit, or Lattice's
         Diamond on an ECP5.

Thank you,
Rick C. Hodgin

Re: VHDL or Verilog?
Rick C. Hodgin:
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two

Visual or graphic entry design tools for HDLs are somewhat out of favour
at the moment. (But not with me !) The only serious one I know (and use
every day) is the Block Diagram Editor in Aldec-HDL. If you want  a tool
just to use you can buy that (Aldec-HDL Desktop edition) for about

it's more than a one man job.
There is  a tool in Vivado but it's not really the same kind of thing.
I find the ability to describe a complex project with hierarchical block
diagrams to be very useful. Since the VHDl (or Verilog) is generated
from the diagrams you get customer friendly documentation that is
actually up to date !

MK

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