Hi,
Can anybody please tell me what is wrong with the following code? In post-translate simulation there are a few unexpected short pulses. Thanks,
Alastair
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity divcontrol is port ( q : in std_logic_vector (7 downto 0); pulse, shift, rstout,ledinc,ledread: out std_logic ); end divcontrol;
architecture BEHAVIORAL of divcontrol is begin
with q select pulse