VHDL language is out of date! Why? I will explain.

Interesting. I now handle this manually by using annoying identifiers for the unsynch nodes. Maybe "run_glitchy" vs "run".

OK here's mine. I get automated mistake-finding at the editor, analysis, and elaboration level of each library unit.

  1. Emacs vhdl-mode completes keywords and identifiers, matches most parens and prompts for clauses in a keyword statement. This prevents most syntax errors from happening.
  2. I run simulation analysis vcom -c mydesign.vhd from an editor function key every few lines of code. This step finds the most errors but puts the cursor right on each one and tells me what's wrong.

I would estimate:

90% syntax punctuation: missing or excess : ; ) etc. 10% static mismatch of code with local or library subtypes. Length, range etc. 10% signature mismatch of code and local or library subprograms

At the top level, Emacs vhdl-make automatically finds units with multiple declarations in the project path, like this: WARNING: Architecture declared twice (used 1.): "synth" of "cnt_decode" 1. in "~/vhdl/play/cnt__decode.vhd" (line 18) 2. in "~/vhdl/play/cnt_decode.vhd" (line 18)

  1. elaboration: vsim -c mydesign will find most runtime mismatches and give a pretty good description of what's wrong. Some messages are more cryptic hints at infinite loops,like
** Fatal: Write failure in vlm process (32,-1)

That leaves the functional errors to simulation viewers and assertions, but I have no automated method for this.

-- Mike Treseler

Reply to
Mike Treseler
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I agree that VHDL has some disadvantages when I comes to syntax features.But if there is not a synthesis tools, I just can=B4t use any other language to program my FPGA.

Reply to
Helmut

Sorry. Let me fix that subject line. I agree with you. The thread went off on a tangent as they often do :)

-- Mike Treseler

Reply to
Mike Treseler

In that perpective, using C would have made much more sense. Most electronics engineers can write software in C. Having to use python is like trading one obscure language for another.

Anyway, I've been using VHDL for a couple of years now (on and off) and I must say it has its disadvantages, but it also is pretty powerfull. I particulary like the functions and records. They allow me to write complex stuff in just a few lines.

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Reply to
Nico Coesel

Thanks for info,

Paul.

Reply to
Paul Taylor

See the extremely bad opinion of Joe Costello as former CEO of CADENCE:

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Archimedes Neutrino

snipped-for-privacy@googlemail.com wrote:

Reply to
reiner

MyHDL is set up as a typical open-source project. It is as open as possible and encourages people to contribute. People do contribute when it's useful to them, and they do so for MyHDL. Of course, there is a benevolent dictator (yours truly) to set the pace and to arbitrate.

So the statement above is disrespectful to all those who contributed in some form to MyHDL. I immediately add that I'll take the blame: I haven't acknowledged these contributions explicitly enough in the past. I'll try to fix that, and I apologize to all those concerned.

now.

doubt, believe, impression ... instead of spreading FUD, why not just tell us about our complaints and the features you are missing. (Not in this newsgroup of course.)

Jan

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Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
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Reply to
Jan Decaluwe

dynamic

projects now.

Aside the obstacles I mentioned in my earlier post, I'm also concerned about the ability of MyHDL to write clever code. I would like to know how you can implement a 16 to 4 priority encoder in MyHDL....

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Reply to
Nico Coesel

Yes, maybe you could create a new group in which to boldly go.

Reply to
MikeShepherd564

Just like you would in VHDL or Verilog: loop over the input bits and break out early as soon as a '1' is found.

No cleverness needed, just an HDL with support for procedural statements.

Jan

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Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
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Reply to
Jan Decaluwe

Whether it is disrespectful or not depends on the view point. For one person or probably a hand full person it is a great effort. I didn't mean it in a negative way.

First of all, I miss sufficient documentation and really useful examples. A large project I think of has some millions gate coded in hundreds of blocks designed by five or more hardware designers with several clock domains and will finally work. It should be able to efficiently simulate, write back synthesis timing information and so on.

I like Python for a long time. Python was not designed for hardware design. The ideal language has the most comprehensive syntax and good support e.g. for parallel processes. It can be done in Python, but with less comprehensive syntax and less simulation performance compared to an optimised language.

Of course, this is only my opinion. I promise I will look over MyHDL again (did it last half a year ago).

Best regards

Wolfgang

Reply to
Wolfgang Grafen

Mr. Decaluwe,

you do great work ! Do not listen any disrespectful troll who has no idea what is MyHDL.

What is still missed on MyHDL page are clear informative examples and tutorials. Current domain name is also bad to remember. Menu structure is also poor.

Thanks in advance!

Reply to
psihodelia

What's wrong with this one?

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-- Mike Treseler

Reply to
Mike Treseler

You did see the examples here - maybe slighly miss-named as cookbook ?

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Jan added fitter reports and mapping results to these examples, and they are quite good.

-jg

Reply to
Jim Granville

My opinion is quite different :-) but let's discuss this further in the MyHDL newsgroup if you want to.

Anyway, this implies that MyHDL is likely to disappoint you. Also, it will probably work better for "agile" hardware design based on programmable platforms than for the mega-asic projects that you are describing.

However, I believe those will become out of date long before VHDL does :-)

Jan

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Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Kaboutermansstraat 97, B-3000 Leuven, Belgium
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Reply to
Jan Decaluwe

No, MyHDL doesn't disappoint me. I will give it another try. I would like to have something Pythonic like MyHDL in my work flow :)

Reply to
Wolfgang Grafen

Yes, I saw it and followed some examples before. Now I remember, I had problems describing and simulating a design composed of several modules. It is only me - I didn't know how to do it and I would like the documentation extended in this way. People who have to decide whether MyHDL will used for a project or not would like to see even more, a proof, e.g. a complete project, multiple clock domains, individual delays on signals (after...ns), asynchronous logic handling come in my mind. The developpers might know MyHDL can do all that, but naturally there is the fear that approaching the top from the bottom a system might fail somewhere inbetween.

MyHDLs documentation is becoming better and better. I honour that.

Just my 2 cents

Wolfgang

Reply to
Wolfgang Grafen

The Motto of MyHDL Project says: "From Python to silicon". Many people are interested to see any clear example of how one can produce a bit file for a FPGA from MyHDL.

For example, it could be an example of binding MyHDL with popular XST, demonstrating, say, simple UART/VGA/LED/ or even SRAM controller. At the same time, VHDL analogous program should be available for the comparison.

In that case, people can compare two digital design flows, executed using different languages. Results will show the quality of synthesized code, expended translation/synthesis time, and maybe will reveal some difficulties.

Of course, MyHDL has preliminary preference because of its simplicity, syntax, and power.

Reply to
psihodelia

The open source motto says: "Try it and see."

That binding is verilog code. Run it through your tools and see if works.

The process of converting verified hdl code into an fpga image is vendor specific. I would have as little interest in hearing about the xst process as you would hearing about quartus.

Open source projects have no marketing department. Such comparisons are done by interested users.

-- Mike Treseler

Reply to
Mike Treseler

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From reading the introduction:

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it will be clear that the MyHDL simulator is just an event-driven simulator, in good old Verilog and VHDL tradition.

Jan

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Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
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Reply to
Jan Decaluwe

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