VHDL is correct but when burn into chip is not correct. Help me to solve this problem please

Did you simulate the circuit after you fit it into the chip?

vax, 9000

This happens all to often.

First thing to check is that you don't have any timing violations. Check the STA report. Next, is it possible that you have a problem with data crossing between clock domains (i.e. could be a problem that means your code is incorrect, but it just doesn't show in the simulation because of the way the clocks are generated. More details on your exact problem would help)?

If you are convinced that it's the synthesis or P&R tools that have got it wrong, then you should try running simultions on the post-synthesis and post-P&R netlists. Alternatively, if you have a equivalence checking tool, you can compare the next lists automatically. You can try synthesizing the design with different optimisation settings to see if the bug changes / disappears. That's quite a good sign that something is wrong with the tools.

Cheers, Jon

No, i simulated code before fit it into the chip

Hello, Jon From timing analysis in Quartus (my circuit have 2 clock) Fmax of first clock that the code can run about 75 MHz and another clock(clk2) can run about 120MHz. the first clock we run at 33.33 MHz (I use this clock to system clock) and the other clk is used for receive external signal. and the recieve frequency i try fist is 50 MHz and found incorrect in the circuit so i decrease recive frequency to 4 MHz and it is still incorrect. (note: clk2 is use to write signal into RAM and Clk1 is used to read signal from RAM). before I ask you i simulate only functional and i will try to simulate follow your suggestion. when i change option to synthesis the result is different. (i.e. sometimes state is not change to correct state, some signal is not change follow i write the code) Thank you for your sugestion before. and hope to recieve your next sugestion. thank you very much.

Cheers, Sunt and Akaporn

What special precautions are you taking for signals that are clocked by the logic on one clock net that are passed to logic that is clocked by the other clock net?

Is your RAM dual port, or are the reads and writes (at different frequencies) using the same port?

Philip

Philip Freidin Fliptronics