Hi, all
Here are two processes: One is temporary buffer to acquire transient / real-time input data; the other is another buffer to store every 11 samples; when 11 samples are filled in ChipBuffer_temp, BufferReady is asserted in the first process.
My problem is : expcept the clock signal ChEst_Clk1x, the BufferReady is also treated as Global Clock in Xilinx Constraints Editer, which is not desired. To my understanding, the signal with rising or falling event will be regarded as Clock...., but here I don't know why BufferReady is put in the Global list , and how can I avoid this ?
Many thanks.
ChipInput: process(ChEst_Reset,ChEst_Clk1x)
begin
if ChEst_Reset = '1' then
ChipBuffer_temp (others => '0'));
ChipCount