VHDL in Xilinx : why this signal is regarded as Global Clock ?

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Hi, all



Here are two processes: One is temporary buffer to acquire transient /
real-time input data; the other is another buffer to store every 11 samples;
when 11 samples are filled in ChipBuffer_temp,  BufferReady is asserted in
the first process.



My problem is : expcept the clock signal ChEst_Clk1x, the BufferReady is
also treated as Global Clock in Xilinx Constraints Editer, which is not
desired. To my understanding,  the signal with rising or falling event will
be regarded as Clock...., but here I don't know why BufferReady is put in
the Global list , and how can I avoid this ?



Many thanks.





ChipInput: process(ChEst_Reset,ChEst_Clk1x)

begin

     if ChEst_Reset = '1' then

                 ChipBuffer_temp <= (others => (others => '0'));

                 ChipCount <= 0;

                  BufferReady <= '0';

     elsif  ChEst_Clk1x'event and ChEst_Clk1x = '1'   then



               if    ChEst_FEPhCtrl =  "01"
       -- BitSync is acquired

             ChipBuffer_temp(ChipCount)  <= ChEst_ChipIn_I;

                         if         ChipCount < 10  then

                                     ChipCount <= ChipCount + 1;

                                    BufferReady <= '0';

                         else

                                      ChipCount <= 0;

                                      BufferReady <= '1';

                         end if;

               end if;

    end if;

end process;



DataAcquistion: process(ChEst_Reset,ChEst_Clk1x)

begin

if ChEst_Reset = '1' then

       ChipBuffer_I <= (others => (others => '0'));

               BitCount <= 0;

elsif ChEst_Clk1x'event and ChEst_Clk1x = '1' then

     if  BufferReady = '1'  and ChEstDone_temp = '0' then

       ChipBuffer_I <= ChipBuffer_temp ;

               BitCount <= BitCount + 1;

      end if;

end if;

end process;


regards,
freedragon



Re: VHDL in Xilinx : why this signal is regarded as Global Clock ?
Hi Jimmy,

We've run into similar difficulties.  The Xilinx tools will assume, by
default, that anything connected to a clock input is connected to a
global clock input.

The workaround is to explicitly connect the input pin to an IBUF
primitive, and connect the IBUF output to everything that uses the input
signal.

For more information, get the Xilinx Libraries Guide.

Here's a link for the PDF version for V6.1 ISE.
http://toolbox.xilinx.com/docsan/xilinx6/books/docs/lib/lib.pdf

Here's a link for the online HTML version for V6.1 ISE
http://toolbox.xilinx.com/docsan/xilinx6/books/data/docs/lib/lib0001_1.html

Other versions are available, but you'll need to search for what you
require.

Best regards,
Dwayne Surdu-Miller


Re: VHDL in Xilinx : why this signal is regarded as Global Clock ?
P.S. I dunno off-hand why BufferReady is deigned to be a global clock.

One way to find out would be to synthesize the module then view the RTL
schematic of the synthesized design and search for anything that
connects BufferReady to a clock input.  If XST found implications that
BufferReady is a clock, the RTL schematic should help you find where the
implications took place.

Dwayne Surdu-Miller


Re: VHDL in Xilinx : why this signal is regarded as Global Clock ?
P.P.S.  It looks like BufferReady should be an output, not an input (my
apologies).  It shouldn't be on a global clock pin at all, as they are
input-only!  Something weird is happening.


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