VHDL help with adding modules

Hey guys, I'm fairly new to vhdl. Trying to test a small portion of an mp3 player to work. Seems that If I add my synchronizer only, Model Sim will show in the simulation that the signals are assigned to the correct values as it should. However If I add another module (bit reservoir) all the signals go to 'U' (undefined) except for clk and reset. However the modules do not share any outputs so that is not a problem. Portion of my code below. Any ideas? thanks.

component synchronizer port( clk : in std_logic; rst : in std_logic; start : in std_logic; done : out std_logic; gr : in std_logic; si : in stream_in_type; so : out stream_out_type; bri : in br_out_type; bro : out br_in_type; frm : out frame_type ); end component;

component bitreservoir port( clk : in std_logic; rst : in std_logic; start : in start_type; bro : out br_out_type; bri : in br_in_array_type ); end component;

begin sync_unit: synchronizer port map( clk => clk, rst => rst, start => start.synchronize, done => done.synchronize, gr => start.granule, si => si, so => so_sync, bri => bri, bro => bro(0), frm => frame );

br: bitreservoir port map( clk => clk, rst => rst, start => start, bro => bri, bri => bro );

-----------------------------clock generator

----------------------------- process begin loop clk