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VHDL help needed ($)

I need to accomplish the following using the Spartan-3 Starter Kit. This is a small part of my overall project and I don't have time to do it.

Inputs-

5V differential quadrature (A+ A- B+ B-) signal Enable (active high) Counter Reset (active high)

Output-

Trigger Pulse (active low)

Specifics-

I need a trigger pulse that is n clocks wide (n should be changeable in code- pulse length will need to range between 10us and 500us) whenever the quadrature counter (24 bit) increments/decrements by x counts (x should be changeable in code and will range from around 15 to 200). Quadrature input max speed is 7.8mhz. The trigger pulse should only be output when the enable signal is active (the counter can run all the time).

I am not asking for free help, I just need a complete solution and I will pay for it ;)

Thanks,

Gary

Reply to
G Swindell
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Hi Gary, I am working in TooMuch Semiconductor solutions

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This is a startup (2 months old) and focuses on providing EDA & Verification solutions. We have experianced engineers in Design and Verification. We can help you do this, and we don't expect anything in return. The work doesn't include any risk/responsiblity from our part. We'll do this design and post it in the groups itself. Thanks & Regards, Naren.

Reply to
Narendran Kumaraguru Nathan

Hi Gary, I waited for you ... I had the following questions in my mind...

  1. Why active high reset? The general procedure is to use active low reset. Did you look @ spartran 3 data sheet to find out wether it has active low reset f/f's or active high reset f/f's?

  1. Is reset asynchronous? It is better to have it.

  2. Do you wish to change N dynamically, over time? o If yes, should N be sampled and used? o If yes, then when should it be sampled. o If no, then sometimes the trigger output 'll not become inactive high.

  1. Do you wish to change X dynamically, over time? The logic is quite complex to implement. If X is static over time (never changes any time), then the circuit gets reduced to a mod X counter.

  2. Is the maximum speed with which A+/A-/B+/B- can change is 7.8 MHz?

  1. What 'll be the dynamics of the enable signal ? Can it change any time ? o If yes, can it change when the trigger is active (low)? o If yes, what should happen to the trigger output? o If no, what is the valid interval when it can make a change ?

  2. What is the maximum speed of the clock? Since the quadrature inputs can change @ 7.8 MHz, the sampling clock should atleast be 7.8 * 2 = 15.6 MHz. Is the speed supported in spartran 3?

  1. Can you visualise the circuit you want? If yes, can you just capture it on a piece of paper and scan & send it to me?

  2. You've mentioned that the counter is 24 bits wide. Is there any specific reason for that?

  1. You've not mentioned on what condition does the counter increment / decrement.

Thanks & Regards, Naren.

Narendran Kumaraguru Nathan wrote:

Reply to
Narendran Kumaraguru Nathan

Gary, Can you post your professors phone number and email so if we have any questions while working your homework, we can ask them directly. :)

Regards, Jim

Reply to
Jim Lewis

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