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VHDL FSM Problem

Iam using 2 process type FSM in my VHDL code the problem is the FSM is not working correctly , It hazards randomly when I checked the syntheizer reprt I founded that

"Using one-hot encoding for signal "

It automatically uses one hot techneque for the FSM

Now , how can I force it to use "gray" type ?

Reply to
H.Azmi
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This depends on the synthesizer you are using. Generally speaking, it can either be done through the synthesizer settings or via synthesizer attributes embedded in the VHDL code. Check your synthesizer's manual.

/Mikhail

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Reply to
MM

I'm quite sure that this will NOT solve the problem ...

check the following:

- all inputs to the state machine must be synchronous to the clock ... that means they must be registered with the same clock before they are used inside ...

- the timing-constraints are correct and met

bye, Michael

Reply to
Michael Schöberl

You might also want to check the clock integrity. double edges can wreck havoc with one-hot fsms (the bit at '1' gets cleared but doesn't offer enough setup time for the next bit to get set, so one-hot is at all 0s).

Reply to
pascal

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