My application needs 4KB (32768 bits) of buffer space for incoming data. We are wanting to use the Spartan-3E, but we have not entirely settled on a version of it. Obviously, we would like to use the cheapest package possible.
My question is if this is too much buffer to synthesize in VHDL. If so, what would be my best option here? The data is written to the buffer 8 bits at a time, and it is used 64 bits at a time.
Currently, I am creating this buffer like this:
type ram_type is array (0 to 511) of STD_LOGIC_VECTOR(63 downto 0); signal data_buffer: ram_type;
However, once I connect it to the logic that uses it, it reports that it's too large for the chip.
Is there a better way to accomplish what I am trying to here?
Thanks!
Alex McHale