Hi.. I have one question regarding xilinx ise webpack. Why it doesn?t give any error of type missing source code . bcoz I tried to run some codes on xilinx ise webpack and then on altera maxpllus II. On altera I was continuously getting messges like missing source code "C0" while the same code was running fine on xilinx tool. the code is : library ieee; use ieee.std_logic_1164.all; entity fib is port (Clock,Clear: in std_ulogic; Load: in std_ulogic; Data_in: in std_ulogic_vector(15 downto 0); S: out std_ulogic_vector(15 downto 0)); end entity fib; architecture behavior of fib is signal Restart,Cout: std_ulogic; signal Stmp: std_ulogic_vector(15 downto 0); signal X, Y: std_ulogic_vector(15 downto 0); signal C : std_ulogic_vector (15 downto 0 ); signal Zero: std_ulogic; signal CarryIn, CarryOut: std_ulogic_vector(15 downto
0); begin P1: process(Clock) begin if rising_edge(Clock) then Restart <= Cout; end if; end process P1; Stmp <= X xor y xor CarryIn; Zero <= '1' when Stmp = "0000000000000000" else '0'; CarryIn <= C(15 downto 1) & '0'; CarryOut <= (Y and X) or ((Y or X) and CarryIn); C(15 downto 1) <= CarryOut(14 downto 0); Cout <= CarryOut(15); P2: process(Clock,Clear,Restart) begin if Clear = '1' or Restart = '1' then X <= "0000000000000000"; Y <= "0000000000000000"; elsif rising_edge(Clock) then if Load = '1' then X <= Data_in; elsif Zero = '1' then X <= "0000000000000001"; else X <= Y; end if; Y <= Stmp; end if; end process P2; S <= Stmp; end behavior; I would like to know what is the addition in xilinx ise which altera maxplus II doesn?t have? Waiting for your reply. Shahabuddin Inamdar- posted
19 years ago