vhdl code : altera vs xilinx

Hi.. I have one question regarding xilinx ise webpack. Why it doesn?t give any error of type missing source code . bcoz I tried to run some codes on xilinx ise webpack and then on altera maxpllus II. On altera I was continuously getting messges like missing source code "C0" while the same code was running fine on xilinx tool. the code is : library ieee; use ieee.std_logic_1164.all; entity fib is    port (Clock,Clear: in std_ulogic;          Load: in std_ulogic;          Data_in: in std_ulogic_vector(15 downto 0);          S: out std_ulogic_vector(15 downto 0)); end entity fib; architecture behavior of fib is     signal Restart,Cout: std_ulogic;     signal Stmp: std_ulogic_vector(15 downto 0);     signal X, Y: std_ulogic_vector(15 downto 0); signal C : std_ulogic_vector (15 downto 0 );     signal Zero: std_ulogic;     signal CarryIn, CarryOut: std_ulogic_vector(15 downto

0); begin     P1: process(Clock)     begin         if rising_edge(Clock) then              Restart <= Cout; end if; end process P1; Stmp <= X xor y xor CarryIn; Zero <= '1' when Stmp = "0000000000000000" else '0'; CarryIn <= C(15 downto 1) & '0'; CarryOut <= (Y and X) or ((Y or X) and CarryIn); C(15 downto 1) <= CarryOut(14 downto 0); Cout <= CarryOut(15); P2: process(Clock,Clear,Restart)     begin         if Clear = '1' or Restart = '1' then             X <= "0000000000000000"; Y <= "0000000000000000"; elsif rising_edge(Clock) then if Load = '1' then X <= Data_in; elsif Zero = '1' then X <= "0000000000000001"; else X <= Y; end if; Y <= Stmp; end if; end process P2; S <= Stmp; end behavior; I would like to know what is the addition in xilinx ise which altera maxplus II doesn?t have? Waiting for your reply. Shahabuddin Inamdar
Reply to
Shahab
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This is a good example of why single letter names are not a good idea. I wanted to search on all occurances of your signal "C". But obviously this would be pointless.

After reformatting the code to make it more readable, I see that C is declared as a vector 15 downto 0, but you never assign a value (or use the result) of element 0. My guess is that the Altera tool was giving you a warning, and then ignoring element C(0). The Xilinx tool was just ignoring element C(0) without a warning. I don't think any synthesis tool would consider this an error unless you have it configured for that.

To fix the problem you can either define C as a vector of 15 downto 1, or assign C(0) a constant value like you did for CarryIn.

One other note; you are creating Restart as a synchronous signal, but using it to async reset X and Y. That will reset X and Y in the current clock cycle (async reset), but will hold it in reset until after the next clock. Is that what you intended? You may have intended to reset it on the next clock edge once Cout is asserted. If so, you can remove signal Restart and replace it with Cout. This will reset X and Y on the same clock cycle as before, but will not hold it in reset for the extra clock period.

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Rick "rickman" Collins

rick.collins@XYarius.com
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Reply to
rickman

This type of warning can be useful. In a recent design parts of an interim scaling process were being optimised out. Checking the warnings told me this and I was able to add a 'noreduce' synthesis attribute to stop it.

Nial

------------------------------------------------ Nial Stewart Developments Ltd FPGA and High Speed Digital Design Cyclone Based 'Easy PCI' proto board

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Reply to
Nial Stewart

Shahabuddin,

I ran this code through ISE/WebPack 6.2.03i (the current version), and I see the following warning issued during HDL Synthesis:

WARNING:Xst:1780 - Signal is never used or assigned.

Any unused or unconnected signal should trigger this warning in XST.

thanks, david.

Shahab wrote:

Reply to
David Dye

Hi You are not using C bit any where in your design. I am not sure why Xilinx and Altera tools are giving different warnings. In both tools they are not implementing the C bit internally. (you can see this through the RTL view provided in quartus and xilinx tools)

Xilinx is giving you a warining so that you can remove that bit from your vhdl file. Altera is not giving any warning but both s/w won't implement that bit

bye bijoy

Reply to
bijoy

hi everybody.

i was just wondering if it is possible for any combinational vhdl code to utilize the same amount of logic cells while optimizing area and speed both?also with the same max. propagation delay in both cases?

the code i tried to run on xilinx ISE webpack 6.2i is:

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all;

entity testarith is port ( Asigned : in signed ( 15 downto 0 ); Bsigned : in signed ( 15 downto 0 ); Cstd : in std_logic_vector ( 15 downto 0 ); Dstd : in std_logic_vector ( 15 downto 0 ); Qab : out signed ( 15 downto 0 ); Mab : out signed ( 31 downto 0 ); Qcd : out std_logic_vector ( 15 downto 0 ); Mcd : out std_logic_vector ( 31 downto 0 )); end testarith;

architecture behv of testarith is begin Qab

Reply to
Shahab47

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