library IEEE; USE ieee.std_logic_1164.ALL; ENTITY dte IS PORT ( rst,dcr,ri,cd,cts,rxd,data,clk: in std_logic; dtr,start,rts,txd,out_dte: out std_logic); END dte;
--INPUT LINES:
--RI: Ring Indicator -> the modem (DCE) alerts the computer of an incoming call
--CTS: Clear-To-Send -> the DCE informs the DTE that it can transmit data
--RxD: Received Data -> it contains the received data
--DCR: DCE Ready -> the DCE is ready to operate
--CD: Received signal line detector -> there are data on the RxD line
--OUTPUT LINES:
--DTR: DTE Ready -> the DTE is ready to send/receive data
--RTS: Request-To-Send -> the DTE informs the DCE that it is going to transmit data
--TxD: Transmitted Data -> it contains the data to be transmitted
--OUT_dte: Output line -> it contains the data received from the DCE for presentation to the user
ARCHITECTURE dte_arch OF dte IS TYPE state IS (st0,st1,st2,st3,st4,st5,st6,st7,st8,st9, st10,st11,st12,st13,st14,st15,st16,st17,st18,st19, st20,st21,st22,st23,st24,st25,st26,st27,st28,st29); SIGNAL present_dte,next_dte:STATE; BEGIN processdte: PROCESS (rst,dcr,ri,cd,cts,rxd,data,clk) BEGIN if rst='0' then --reset logic low asynchronous present_dte dtr