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VHDL Beginner: Reset a counter (instead of "000000000....000000") - better way ?

Hello,

i have a counter which is 27 bit long.

signal counter : STD_LOGIC_VECTOR(26 downto 0);

Is there a "better" way to reset than counter

Reply to
Martin Maurer
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Martin,

If your signal "counter" is declared as an integer with a valid range you can then use a reset as shown:

signal counter : integer range 0 to 67108863 := 0; ... if reset = '0' then signal counter Hello,

Reply to
Jason Berringer

Reply to
Allan Herriman

Allan & Jason B. show the typical ways; alternatively, if you are using numeric_std, you could write:

counter

Reply to
jtw

Personally, if I'm doing a counter I would use an unsigned type (or even an integer!) rather than "casting" to std_logic_vector all the time. After all, what you're representing is a number...

Cheers, Martin

--
martin.j.thompson@trw.com
TRW Conekt, Solihull, UK
http://www.trw.com/conekt
Reply to
Martin Thompson

Hi,

Here's a different but similar question: Is there a better way to do the following (vector extension):

signal A,B: std_logic_vector(10 downto 0); signal X: std_logic_vector( 7 downto 0);

A Jason T. Wright

Reply to
Rajeev

Reply to
Michael Schöberl

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--Ray Andraka, P.E. President, the Andraka Consulting Group, Inc.

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Reply to
Ray Andraka

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