Attached is my first cut at an address decoder. While it works I am not sure it's the best method. Also I am not sure why there are four 4:1 muxes in the design.
Any help or ideas?
Thanks, JTW
entity Decoder is
Generic ( ASIZE : integer := 32; BSIZE : integer := 12);
Port ( clk : in std_logic; rst : in std_logic; address : in std_logic_vector(ASIZE-1 downto 0); reset_stb : out std_logic; reg1_stb : out std_logic; reg2_stb : out std_logic; reg3_stb : out std_logic; valid : out std_logic); end Decoder;
architecture Behavioral of Decoder is
constant PMC_ADDR : std_logic_vector := X"00008"; constant RESET_ADDR : std_logic_vector := X"000"; constant REG1_ADDR : std_logic_vector := X"004"; constant REG2_ADDR : std_logic_vector := X"008"; constant REG3_ADDR : std_logic_vector := X"00C";
begin
process (clk, rst) begin if rst = '1' then
valid