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VHDL 2 dimension array

Hi,

I am just beginner of VHDL. I want to define a 2 dimensional input variable in entity. I think the syntax is something like this:

v : in std_logic_vector(2 downto 0)(11 downto 0);

Please advice. Thanks!

Reply to
eeh
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first you create a type.. then assign it... type v_typ is array (2 downto 0) of std_logic_vector(11 downto

0); signal v: v_typ

now you can access it as v(i)(j) Hi,

Reply to
Simon Peacock

Simon he's asking about how to use multi-dimentional arrays in port declaration. not for signal/variable declaration.

Rgds, Karthik

Sim> first you create a type.. then assign it...

--
Karthikeyan Subramaniyam,
Verification Engineer,
TooMuch Semiconductor Solutions Pvt. Ltd.
www.toomuchsemi.com
A Bangalore based startup specialising on services in EDA & Verification.
Reply to
Karthikeyan Subramaniyam

Very Thanks!

Reply to
eeh

The same theory works anywhere.. in the case of an entity.. you put the type in a header and use the "library" string :-)

I use the same thing in entities, processes and generates.

Simon

downto

Reply to
Simon Peacock

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