VHDL

Hey

i am pretty green at this VHDL...

can someone tell me the error in this code.. :

library IEEE; use IEEE.STD_LOGIC_1164.all; use ieee.std_logic_unsigned.all;

entity Test is port( b: in std_logic; a: out std_logic_vector(7 downto 0)); end Test;

architecture eksempel of Test is signal a_old,a_new : std_logic_vector(7 downto 0); begin

test_if:process(b) begin

if b='1' then a_new

Reply to
Repzak
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[...]

I would say your code adds 1 to a_old ... your problems are:

- a_old is not set ... there is no startup-init nor any other assignment

- what should be the output of A if b = '0' ?? you need a flipflop description for a counter if rising_edge(b) a_out

Reply to
Michael Schöberl

I believe that the phrase: a_new

Reply to
Don Golding

Hey...

Thats defentlig true...

i also have some books and some urls, but a lot to take care of in the first place

i need more some simple code... btw i am using protel / nexar...

but there are so much to read, i need to get going a litle to try and read and try...

i think i got some of the problems...

my next is pushbutton bouncing... ):

Kasper

Reply to
Repzak

I think that's the problem as well. You could use:

a_new

Reply to
C

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