Hey
i am pretty green at this VHDL...
can someone tell me the error in this code.. :
library IEEE; use IEEE.STD_LOGIC_1164.all; use ieee.std_logic_unsigned.all;
entity Test is port( b: in std_logic; a: out std_logic_vector(7 downto 0)); end Test;
architecture eksempel of Test is signal a_old,a_new : std_logic_vector(7 downto 0); begin
test_if:process(b) begin
if b='1' then a_new