Very simple VHDL problem

You can't use IF outside of processes, a bit like that you can't use the C IF outside of functions. You could write it like this:

led

Michael a écrit :

Hello There are a few points that need clarifying, besides you "unexpected if" problem which has already been dealt with.

NEVER, in any case, use these non-standard libraries called std_logic_arith, std_logic_signed and std_logic_unsigned. Use numeric_std instead. With this library, declare your signal cnt as unsigned instead of std_logic_vector

Your if statement should be inside a process, as has already been said. Second point : signal switches is an array of std_logic, not an array of integers. std_logic litteral constants must be written betwen single quotes: if switches(0) = '0' then led

Hi Frank - thanks for clearing that up. I had not realized that limitation of IF. Why can ifs only be used inside processes? That strikes me as an odd limitation, though I'm sure there's a good reason behind it.

I tried your suggestion for the change, but I got this error: "can not have such operands in this context.". That strikes me as an odd error

- as led, cnt, and enccnt are of the same type.

Any idea what is wrong? Thanks again!

-Michael

Hello again - I took Nicholas's suggestion to change the comparison to: switches(0)='0' (I added single quotes around the 0) - and that fixed the problem. The code synthesized properly and is now running as expected on my Spartan-3E dev board! Thanks!

-Michael

I don't know if there is a reason, sometimes VHDL looks a bit random to me, e.g. I always forget where I need a semicolon and where it is forbidden. Maybe the language designers have designed the IF/WHEN difference, because IF doesn't need an ELSE, but then you need a latch and WHEN is pure combinatorial logic.

See the other answer: Unlike in C (char/char*) you have to use '0' instead of just 0 for elements of std_logic_vector (and e.g. "010" for a "string").

Hello again - I took Nicholas's suggestion and put single quotes around the '0' in the switches(0)=3D'0' comparison - and now it works exactly as expected! Thanks!

-Michael

Hi Nicholas! I must admit I did not make a conscious choice to use those libraries - they were put in automatically by Xilinx ISE. So you're saying for my purposes, that section should just look like this?:

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.numeric_std.all;

s:

So is a cast in VHDL just like a cast in C? I must admit this is the first I've heard of VHDL having that ability.

Thanks!

-Michael

Hi Michael, This might help you... Cheers, Syms.

Frank Buss wrote: (snip)

If you use verilog, the ?: operator is just like the C operator!

-- glen

Michael a écrit :

In VHDL you can only cast between "closely related types". You can not cast an integer to a signed vector, for example. This requires a conversion function.

In the previous example, I used a cast to convert an unsigned to a std_logic_vector. This is allowed because both types are arrays of std_logic.

Nicolas

It may be to remind you that - within a process - you can treat VHDL as a programming language with all the limitations of sequential programming like C (at least for simulation, though for synthesis you have to obey further restrictions; e.g. no files!), but outside a process you are in a completely different paradigm, closer to dataflow or functional programming (FP) languages, where you can directly express parallelism (such as interactions between sequential processes).

It's quite funny because with the arrival of multicore CPUs, the C programming community (along with the rest of the sequential mindset) are talking like there is some kind of crisis! They will either have to look back a quarter century or so for solutions like Occam, CSP or even Ada's tasking, or adopt something more like VHDL to exploit today's commodity CPUs to more than 1/4 of their capacity.

- Brian

Yes, my son--you are quickly learning the lameness of VHDL. A number isn't a number--sometimes it must be in single quotes, sometimes in double quotes, and most often expressed in binary, just as the ancients used to write. And almost never can you use a number directly, but must convert it from one arcane type to another. -Kevin

On the first day, the VHDL gods created 'integer', 'natural', etc. and created ways to easily specify such numbers in any base, and saw that it was good...and the VHDL gods said, go forth and use these types for they are of my creation and they are good....but the unbelievers who think every number will potentially be bigger than 32 bits on each and every design that they create and the scallywags that created std_logic_arith refused to use 'integer' and instead used std_logic_vectors to perform arithmetic and then cursed the VHDL language for the numerous type conversions that they themselves brought down upon themselves....

KJ

very good :-)

Hans

There is some truth to that. I am usually hamstrung by requirements such as "all ports must be std_logic_vectors", which is a human failing and not technically a shortcoming of the language. Nonetheless, I prefer a language which never requires cumbersome conversions and yet will simulate x's and z's if I need it to. -Kevin

I use std_logic_vector on top ports, but never inside. This is not much extra work.

For me, it's worth some trouble to to be able to do integer, signed and unsigned math in the same module.

-- Mike Treseler

While I also don't like archaic conventions such as requiring SLV on all ports, I prefer a language (VHDL) that catches and identifies problems with conversions, data widths, etc. before simulation. If I have to get a little more verbose, (and get a lot more flexibility in the bargain), that is time well spent.

Andy