Verilog VPI

Hi,

I'm developing in verilog (Xilinx web pack with Modelsim XE). I came to the point I have to use some external c software for generating some signals. It's not mine though but I have the source that is using VPI. The problem is that this external code is using internal static variables for storing data between calls (y[n] = f(x,t,y[n-1])) from verilog and while using only one instance like this

always @(posedge clk) out = $gen(parameters)

it works fine. But now I need to use two or more instances at the same time like this:

always @(posedge clk) out1 = $gen(parameters) out2 = $gen(parameters) . . outn = $gen(parameters)

Because of internal static variables used in gen this is not working any more. I tried to save data like in workarea example (chapter 6)

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but it doesn't work: every time gen function is called different handler is passed to the function and diferent workarea is created on the stack. How can I get module handle that called my C function so I can save data between calls from verilog?

Thanks, Slawc