We need to code some modules in both VHDL and Verilog and would like to use a parameter/generic to control inferring sync or async resets. Is there a clean way to code this that is similar in both VHDL and Verilog?
For example, we could try to use `define in Verilog, but this won't port well to VHDL. I don't see how wen can use generate statements in Verilog to do this nicely, either.
Any thoughts?
Thanks!
John Providenza