Prior to a few years ago, my design style would have been pretty much applicable to either language with little impact, even though I use vhdl.
However, in the last few years, I have started using variables instead of signals in vhdl, the former being akin to blocking assignments in verilog, but without the accompanying race-condition risks associated with verilog. The resulting descriptions are much more like SW, in that when a variable is assigned, it is immediately updated, and subsequent references to it are to the updated value. With VHDL signals, or Verilog non-blocking assignments (the most commonly used kind), the code looks like SW, but does not read or execute like it because of the magical postponement of the updates.
I now tend to use single, clocked processes within an architecture (akin to a module in verilog), with variables for everything, registered or combinatorial, except the IO. Granted, Verilog would also work if I used the same style, but it is way too easy in Verilog to use the wrong type of assignment when you are using both kinds, and there are no protections against doing so. In VHDL you cannot do a blocking assignment to a signal, and you cannot do a non-blocking assignment to a variable. Since a variable cannot be read by another process, there is no chance of a race condition.
Both languages are completely capable of describing virtually any digital logic system that is possible to build (and quite a few that are not!), but it boils down to a particular style, and the pros and cons of that style for a particular user, customer, or organization.
Andy