Hi all,
I'm trying to generate 32 16bits registers using verilog generate :
reg [15:0] Data_reg [N_REG-1:0]; reg [N_REG-1:0] DataSelFlag; reg Data_reg_RST; reg Data_reg_LATCH ;
genvar i; generate for(i=0;i
- posted
17 years ago
verilog genvar, and 2D array access
Loading thread data ...
- Vote on answer
- posted
17 years ago
Re
In fact, I was reading my post, and I've seen my error! So Sorry for the post, this was the line : Data_reg[i]=16'b1; The good line is Data_reg[i]={16{1'b1}};
This is my biggest probleme between verilog and vhdl, verilog is not typed like VHDL..