Hi,
I'm getting some strange results from the simulator that I don't understand (tried both iverilog and ISim).
The design tries to make a combinational assignment inside a module:
module gate (input [1:0] mux, input [17:0] a, output [17:0] b); assign b = (mux == 1) ? a : 17'hx; endmodule
What happens is that "a" never gets through to "b". A similar line outside a module works. With some time scale settings, it works also. The simulation is completely algorithmic, no delays, device models or the like.
Does anybody have an idea, what is going on here? Is this a delta-cycle problem, am I missing something fundamental here?
Apologies if the answer is obvious, but usually I I stick to the safe path of fully synchronous logic in Moore machines...
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