I wonder if it is possible to synthesize on one chip VHDL and Verilog IP cores. I suppose the VHDL to Verilog or vice versa translator could be used. Ideas are welcome.
Remis
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Can't you do that with Synplify? If not, you can always synthesize blocks of, say, VHDL, separately and then instantiate them as EDIF black boxes in the Verilog design.
-Kevin
You can usually do mixed language if you are prepared to pay lots of money for licenses. But if your doing Xilinx, or maybe something else, then have a look at the second method outlined here
You can also use ISE toolset to write out a module in another language. It is there mainly for simulation but you can use it otherwise.
John Adair Enterpoint Ltd.
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Current versions of Xilinx XST, Altera Quartus, and Synplify Pro all support mixed verilog/VHDL designs.
David
You can use both at once in the current version of XST.
Regards, Allan.
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