Vendor supplied symbol/part models?

Hi folks,

Doing a board design with a 456 pin Xilinx FPGA, I find myself in the laborious and potentially error-prone process of building a symbol, footprint and part model from scratch. I am aware that commercial part libraries are available, but we are a university department and don't have those sort of $$$ to throw around for small-run custom designs.

Anyway it seems to me that it would be in vendors' interests (Xilinx in this case) to provide verified symbol and footprint models for major design tools (Mentor, Protel etc)? A quick search of the Xilinx web site didn't turn up anything.

Is there some point I'm missing here, or are my expectations unreasonable?

Regards,

John

Reply to
John Williams
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Most people want the schematics to be somewhat readable. That usually means breaking a 456 pin part up into several boxes. So I doubt if a vendor could provide a generic library part that would work for your design. (Yes, they could do the footprint.)

It would be nice if there were a script/program that would take an intermediate file and make both the schematic library parts and the pin constraints file for the FPGA. Or something like that - the idea is to make sure they were kept in sync.

My suggestion would be to just do it by hand and carefully check things. Then get a couple of friends to help you check it again. It would be worth bribing with beer/pizza and/or offering to trade roles when their design needs checking.

What I've done on many occasions is to collect paper copies of all the data sheets and net lists (both by net and by part/pin) and all the other info you think might be interesting, and take over a conference room with a big table and do a check-everything level design review just before the board goes out. And gerber plots and ... Get somebody to check everything you can think of to check. They don't have to know much about your design, just have enough experience and common sense to read the data sheets and schematics and see if the connections make sense. (Double-double check the bubbles/inversions.)

There is a lot of regularity in the footprint. Assuming your board level CAD system has some sort of scripting, you can probably write a program/script to generate a script that will make the part.

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Reply to
Hal Murray

Well ... about 18 months ago a project I was working on was seriously stalled due to this very issue. An engineer working with me spent no less than 18 hours working on defining schematic symbols and pcb footprints for just ONE large device. Part of the problem was that the EDA tool --maybe I should say "most EDA tools"-- failed miserably at having any intelligence about this process.

The real problem, however, was that, if you ever need to edit, modify, re-use the part and, maybe, slice the pin set in a different way, you would be up for another frustrating EDA library maintenance marathon. A typical examplet that I had to face was migrating a design from something like a

2V1000 to a 2V500, where the footprints have a downward migration path.

Anyhow, to make a long story (about three months work) short, I wrote a Windows application that allowed me to fully describe any component quickly. From that it's pushbutton to generate footprints, schematic symbols and a constraint file. Once all the IO for a component is entered, it is an easy matter to re-slice it any way you want. You can, for example, slice an FPGA to create separate schematic symbols for each bank, or merge banks, etc. As a benchmark, I can do an 456 pin FPGA in about 20 minutes, starting from scratch and finishing with pcb and schematic symbols. More imporantly, moving pins around or even totaly redoing the assortment of pins on the schematic symbols is a no-brainer after the intial work is done.

In general terms, I developed a very low opinion of EDA tools, as it seems that those writing the code seldom have to use it for anything more than the few trivial examples that ship with the tools. I think it's fair to say that, today, you can spend $10K on a tool and fully expect to get unusable libraries and crippled library creation and maintenance tools.

Maybe the OP can grab students from the Computer Science department and put them to work on a generalized component creation utility like what we built. I wish I could provide you with this utility, but it cost a lot of money to develop and I now consider it both a proprietary tool and a competitive advantage in many ways.

I wish chip vendors would agree upon a component decription language/database format of some sort. These files could be published and CAD data very easily derived from them. That would be very useful.

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Reply to
Martin Euredjian

Of course - with a Xilinx part, breaking along IO bank lines, plus one for power, and one for config etc, is a pretty sensible approach. But I do take your point.

I actually did find a symbol for the part buried deep in the mentor/expedition libraries, however it was monolithic, and the pin layout/ordering was, as best i could tell, random.

And doesn't the "A" in EDA stand for "automation"?? ...

I'm pretty new to PCB design and so on, but have been repeatedly warned by several experienced designers "do not trust the library parts"...

Ha - student labour! This approach can be a bit hit and miss...

That's cool. It's not looking too bad - I'm about 4 hrs in, have done the schematic symbols, now doing the pin numbering. I should be done by the end of today. Happily my design is cleanly fractured along IO bank lines.

Some existing standard like EDIF might be able to support this already.

Regards,

John

Reply to
John Williams

Yup. I relax a bit after I have successfully used a part on a design.

It helps to check the raw gerber files to verify that they make sense. (The idea is to catch pin numbering errors and/or right/left top/bottom mirroring errors.)

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Reply to
Hal Murray

Apologies if this is of no use (my third post in FPGA land). Is

formatting link
of any use?

Cheers

Mike

Reply to
mikegw

Mentor have this - it's called Boardlink. It reads the PAR tool output and then can automatically, or with guidance, create a fragmented set of symbols for use in your schematics.

They also have Boardlink Pro which allows you to do pin assignment upfront in a nicer place than either PACE or Altera's pin assigment GUI (that's their claim, I haven't used it :-)...

And RS232 Tx and Rx :-)

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Reply to
Martin Thompson

Hi All, I also use bits of Perl script to produce a text file which lists 'nets connected to the device' next to 'device pin names'. The Perl get the data from the CAD tool netlist output and Xilinx's pinlists. (I used to cut and paste pinlists from the PDF but I think Xilinx provide these files nowadays). This makes it easier to go through the design and look for typos/errors. The Perl also lists unused pins, which catches mistakes too. Also, the script makes the pin LOC bit of the UCF file, the net names on the schematic must match the top level Entity port names, of course. cheers, Syms.

Reply to
Symon

It didn't end up taking very long, maybe 5 hours I suppose. In my youth (!) I entered pages and pages of hex by hand from computer magazines - those old skills came flooding back to me yesterday as I trolled one line at a time through the pinout sheet, checking off each pin and so on...

I should look into this - I'm using Mentor's DesignView and ExpeditionPCB, presumably they have some scripting capabilties.

Thanks for your reply.

John

Reply to
John Williams

Lots of luck - the Expedition flow has zero scripting capability :-)

We use the same flow, and I ended up writing some perl which read the Altera .pin file, created a symbol (using acmaker), then created a PDB entry in hkp, then HKP2partsdb it into the local parts database. Not pleasant, but it meant that changing the pinout of our 2x356 BGAs (it was a while ago - I thought they were scary then :-) was a whole lot less hassle.

If you're using that flow, I'd look into Boardlink (which you have included with your DesignView license - or maybe Boardlink Pro, which costs money.

Cheers, Martin

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Reply to
Martin Thompson

I think the BSDL files for Xilinx parts come close, having a lot of the required information in mmachine-digestible form.

- Brian

Reply to
Brian Drummond

Some time ago I needed a symbol for a 1152 pin virtex2 which easily showed which pins were not used for smaller devices. Xilinx don't even give the data, you've got to superimpose every size you want before you even start up the schematic tool.

I posted to this newsgroup about it, a thread didn't get going but I had a direct correspondence from the Xilinx guy documenting SPARTAN n (can't remember which). Turns out that he had done it properly allready.

If you are lucky you are using spartan n and you can use the excell version of the pin table. If you are very lucky you can import excell into your symbol editor. I use ORCAD, it isn't documented but you can easily paste (shift insert) into the symbol editor.

Rob

Reply to
rob d

Xilinx has Excel spreadsheets with pinouts for many of their chips; they help a lot.

The Pulsonix software I use has a part generator import facility that removes a lot of the hard work when working with large chips. I've written a Perl script that generates an input file from text extracted from a PDF file into an Excel spreadsheet, this saves even more time.

Leon

Leon

Reply to
Leon Heller

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