Hello,
I have two some basic questions about the use of variables inside processes in VHDL and about the processes execution.
I would like to know if the variables will keep the last value each time a process is executed. During the simulation this is the normal behavior, however, I would like to know if the same will happen inside the FPGA device. I have read contradictory opinions about this topic on the Internet..
Also, I would like to confirm if when the FPGA starts all my processes will execute once and then each time an event occurs on any signal in their sensitivity list.
Thank you very much, Fabio