Variable problem

Hi all

I am new to vhdl and xilinx ise. I can generate the waveform for the code (no syntax error) but it produces an error whenever i try to run xpower from the project navigator.

arch xxx of xxx ... variable test; ...

for i in 0 to test-1 loop -- error generated states tat variable cannot be used for range ...

end arch;

however no error occurs if i do it the following method:

arch xxx of xx

for test in 0 to 10 loop ... for i in 0 to test loop ... end loop; end loop; end arch;

the question is if i do not use variable for the 1st mtd; hw else can i do to get rid of that error. Is there a data type which i can use to make it work? or is there something which i overlooked?

tks for any help ywz

Reply to
ywz.oct13
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The variable declaration must be inside a process and must include a type. See the testbench here:

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Reply to
Mike Treseler

Hi Mike,

Sorry for the vague code, below is a more complete version:

... PROCESS (clock) variable msgNum: Integer := 1; BEGIN ... for i in 1 to msgNum-1 loop -- this statement generates an error "variable cannot -- be used for range" when generating power -- report using Xpower (possibly during synthesize) ... end loop; ... end process; end architecture arch;

Any solutions would be greatly appreciated. Thanks ywz

Reply to
ywz.oct13

  1. You don't need a declaration for an integer loop variable, and I expect that commenting that line will eliminate the error.

-- variable msgNum: Integer := 1; -- comment out this line

  1. Note that variable and signal initializations are ignored for synthesis. -- Mike Treseler
Reply to
Mike Treseler

Hi Mike,

for i in 1 to msgNum-1 loop -- msgNum is used as a range for variable "i"

commenting the declaration does not seem to work. The error generated suggests that variables should not be used in range as the synthesis tool is unable to allocate resources as range is not fixed (is that the case??). How should I approach the problem then?

Another question (not related to the above): I need a shared variable 2 dimensional array for some concurrent processes which will update this array; however from what I read, shared variables should not be used for synthesis. What and how should I replace the shared variable with? signals??

Btw, do you happen to know of any links where i can read up about the very basics of vhdl and synthesis?

Thanks again. ywz

Reply to
ywz.oct13

In the future, please post questions like this to comp.lang.vhdl

Maybe msgNum is not declared properly: constant msgNum : natural := 16;

Without a simulator: trial and error. look up some examples, open a book, google, edit code, compile, repeat.

With a simulator: run a sim.

True. By the way, that should be a synchronous process.

With a single process design, you can use a regular variable array. See the examples I referenced earlier.

Google is your friend:

-- Mike Treseler

Reply to
Mike Treseler

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