I have been tetsing with Xilinx V5 LXT board for transceiver evaluation. Currently I am focusing on the transmitter to determine channel alignment. This particular board has 16 transceivers. We programmed them in a generic operational mode with 8b/10b disabled and data rate of 3.125Gbps. For this one board we are seeing that 13 channels are aligned within 60 ps while the 14th channel is off by about 200 ps. It will be great if all channels were with 60 ps. We also did some jitter measurements of data with respect to 1.6GHz clock generated by one of the Xilinx Transceievrs. Preliminary results show that the effective eye opening from the transceiver is .7609 UI. These channels have 4? of trace to the SMA connector. So if we have a long trace to the receiver then the eye opening will be slightly lower then this. I have couple of question for the transmitter portion.
(1) Do you think that we should not have one of the 14 channels misaligned by
200ps?(2) Is there any thing we can do to get better transmit eye opening then 0.7609 UI? Our receiver has requirement of 0.75 UI. My concern is that when we get the V5 FXT device then this number will get worst at higher data rates (> 3.2 Gbps)
On the receiver side, I have couple of questions:
(1) Can the CDR lock on the reference clock?
(2) If yes to question 1, then we are thinking that we can provide the divided reference clock from the forwarded clock. For 3.2 Gbps operation the forwarded clock will be 1.6 GHz. We can divide this clock down to the valid reference clock frequency that the CDR can take. Can this work? Our purpose is to use this in lab environment and not for very long duration.
(3) Is there any way we can program the phase interpolator for each receiver? This can be used for clock alignment purposes during training. If so it will be good to get some details.