Hi *,
on one of our next boards, I'd like to use the Virtex5 feature to have it program itself from an external SPI flash. In that case, the FPGA will provide the SPI clock via the dedicated CCLK pin.
What happens to the CCLK pin after configuration is done? Will it go to tristate or still be an output with permanent '0' or '1'?
The thing is that I want to use the remaining space in the SPI flash from a microcontroller that is also on the board. The uC then would be the master to the SPI flash after configuration and would have to drive the SPI clock, but this only works if CCLK goes to tristate.
There's other ways to do this (like hook up the SPI flash to the uC and have that load the FPGA and such), but the most "elegant" solution would be to just connect flash and uC to the SPI and switch masters on the bus after configuration, if that's possible.
Another "problem" is that I also want to have an SPI slave interface inside the FPGA, to set up registers and such via the uC. Since I can't use the CCLK pin as a clock input later on, I'd have to connect the SPI clock from the uC to another pin on the FPGA. So basically I'd have a clock trace that goes from uC to SPI flash and then on the FPGA to the CCLK pin an another clock pin. This line would have to be driven from the FPGA during configuration and from the uC later on.
Certainly not optimal from a signal integrity point of view, but has anyone tried this?
cu, Sean