V5 Configuration via SPI

Hi *,

on one of our next boards, I'd like to use the Virtex5 feature to have it program itself from an external SPI flash. In that case, the FPGA will provide the SPI clock via the dedicated CCLK pin.

What happens to the CCLK pin after configuration is done? Will it go to tristate or still be an output with permanent '0' or '1'?

The thing is that I want to use the remaining space in the SPI flash from a microcontroller that is also on the board. The uC then would be the master to the SPI flash after configuration and would have to drive the SPI clock, but this only works if CCLK goes to tristate.

There's other ways to do this (like hook up the SPI flash to the uC and have that load the FPGA and such), but the most "elegant" solution would be to just connect flash and uC to the SPI and switch masters on the bus after configuration, if that's possible.

Another "problem" is that I also want to have an SPI slave interface inside the FPGA, to set up registers and such via the uC. Since I can't use the CCLK pin as a clock input later on, I'd have to connect the SPI clock from the uC to another pin on the FPGA. So basically I'd have a clock trace that goes from uC to SPI flash and then on the FPGA to the CCLK pin an another clock pin. This line would have to be driven from the FPGA during configuration and from the uC later on.

Certainly not optimal from a signal integrity point of view, but has anyone tried this?

cu, Sean

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Reply to
Sean Durkin
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Sean,

USR_ACCESS_VIRTEX5

in

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page 92:

"The STARTUP_VIRTEX5 block has inputs that allow the user to take over the CCLK and DONE pins after the EOS (End-Of-Startup) signal is asserted."

Not sure, but this sounds like what you need?

Austin

Reply to
austin

That all sounds reasonable, but be very careful about signal integrity on that big, possibly stubby, clock net, especially where it becomes "another clock pin." Any mistermination plateau, or a slow (a few ns slow!) or ringy clock with a little crosstalk, can make trouble. Unless the situation is perfect, we put a tiny-logic schmitt adjacent to any FPGA clock that we're driving, including CCLK if the fpga is in slave serial mode.

John

Reply to
John Larkin

Thanks for the quick reply. Yes, that should work. STARTUP_VIRTEX5 has an input that enables me to tristate the CCLK pin ater configuration, which is exactly what I need.

cu, Sean

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Reply to
Sean Durkin

Sean,

The other post on the subject is also appropriate: the signal integrity of whatever you do needs to be addressed, as the CCLK signal is not only an output to the SPI flash, the CCLK signal at the pin is also used internally (it is also an input).

Also, there is a note that the CCLK always has a weak pullup, so even while tristate, the weak pullup is still there.

Austin

Reply to
austin

Hyperlynx will tell. ;)

I just noticed that it says the internal oscillator runs at about 50MHz, that's quite a lot faster than I expected...

cu, Sean

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Reply to
Sean Durkin

Hi Sean,

The 50MHz (nominal) free-running internal oscillator (CFGMCLK) is used by the FPGA for House Cleaning during the power up sequence. See UG191

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PP. 21 "Clear Configuration Memory".

A different oscillator is then used during Master mode configurations like SPI after INIT goes high. This clock (Master CCLK) starts off at a slow frequency in the low MHz and is then bumped up to a user-selected frequency. See bitgen -g option "ConfigRate"

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-m

Reply to
Max Baker

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