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V4FX60, hard temac, MPMC2 and SoDIMM

Has anyone instantiated a MPMC2 interfaced to a SoDIMM and the following ports:

1) ISPLB (for the ppc405) 2) ISPLB (for the ppc405) 3) an OPB 4) a CDMAC for the hard temac

When I try the build, if timing based mapping is used, the mapper dies when it tries to route the clocks saying that too many clocks are trying to enter the same clock domain. If I don't use timing based mapping, the same error occurs during PAR (duh).

We're essentially trying to recreate what would be the GSRD setup on a V4FX60, but with an external SoDIMM chip. All of the FPGA is being clocked by an external 100MHz clock. The DDR SoDIMM is being run at

100MHz as well.

For the clock report generated by the error, we can't find a clock region that would have too many clocks in it. In fact, the most the report shows is 4 (or 5) out of 8 global clocks in a region.

Thanks, Mike

Reply to
morphiend
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Try locking down some of the BUFGs. Also. MPMC might have a problem placing IDELAYs, which might lead to clock routing issues, and sometime to non-working MPMC as well. There is an Answer Record showing how to modify the MPMC code to have them placed explicitly. And, in FX60 it makes sense to lock which TEMAC and which PPC are used, strangely enough the tools tend to use PPC and TEMAC, which are far away, which again leads to clock routing issues...

/Mikhail

Reply to
MM

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