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V4FX100 PowerPC PLB issues (and EDK 9.2)

Anyone ever run into an issue where the PowerPC can write to entities on its DPLB, but cannot read from them?

I've added chipscope to the PLB and everything looks right from the control lines. I singled-stepped the first read instruction on the PowerPC and after stepping that instruction the PPC goes off into 'la- la' land.

My system consists of a PPC w/ Instruction side and Data side OCMs, a PLB attached the DPLB0 port, a MPMC3, interrupt controller, uartlite, and host I/F for the TEMAC attached to the PLB.

Reply to
morphiend
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some (maybe all) Xilinx memory cores for DDR2 will go la-la land on read accesses when the memory controller misses DQS strobe from the memory chip once. But in that case the PPC should go la-la also on instruction fetched from the MPMC3

So it is possible that there is some problem with the memory controller or timings or UCF file, etc

Antti

Reply to
Antti

Right now, the problem occurs not only on a memory access, but the TEMAC attached to the PLB. Also, I'm only using the DDR, not DDR2, for the MPMC. From what I saw from via chipscope, the memory controller was properly behaving as I expected (the same as the TEMAC).

Reply to
morphiend

I've seen that. If a PLB read doesn't complete, the PPC locks up pretty solidly. At least one case was a host bus access via a plb_temac (the indirection to the host bus may be important because it's slow or buggy or may be a red herring). The problem I saw didn't happen every time, and could be dramatically reduced with minute timing changes to the PLB accesses.

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Ben Jackson AD7GD

http://www.ben.com/
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Ben Jackson

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