Greetings,
I want to know the input setup/hold and clock-to-out times for LVCMOS18 fast
16mA for an LX40-10 part, and I'm not 100% sure that my interpretation of the data sheet quantities are correct. With V2/V2Pro, the information in the data sheets seemed more straight forward.Here's how I think the input setup/hold and clock-to-out times are calculated. I've used the latest V4 data sheet from the web (Virtex-4 Data Sheet: DC and Switching Characteristics DS302 (v1.12) March 22, 2006) -
----------------------------------------------------- Input setup/hold time:
Page 45 says that for an LX40-10 part the system synchronous (no input delay) setup/hold time, for LVCMOS25, is 1.50ns/-0.46ns. Now, there needs to be an adjustment of the setup/hold time for LVCMOS18. Per page 22, Tiopi is 0.88ns for LVCMOS25. Per page 23, Tiopi is 1.25ns for LVCMOS18.
I would assume that one would now subtract Tiopi for LVCMOS25 from that of LVCMOS18 and then add the difference to the system synchronous LVCMOS25 setup time, and subtract the difference from the hold time, in order to calculate the system synchronous LVCMOS18 setup/hold time:
LVCMOS18 setup time = 1.50ns + (1.25ns - 0.88ns) = 1.87ns LVCMOS18 hold time = -0.46ns - (1.25ns - 0.88ns) = -0.83ns
Is this correct?
----------------------------------------------------- Clock-to-out time:
Page 43 says that for an LX40-10 part the system synchronous global clock input to output delay, for LVCMOS25 fast 12mA, is 3.32ns.
Now, there needs to be an adjustment of the clock-to-out time for LVCMOS18 (fast 16mA). Per page 22, Tioop is 2.43ns for LVCMOS25 (fast 12mA). Per page 23, Tioop is 2.27ns for LVCMOS18.(fast 16mA)
I would assume that one would now subtract Tioop for LVCMOS18 (fast 16mA) from that of LVCMOS25 (fast 12mA) and then subract the difference from the system synchronous LVCMOS25 (fast 12mA) clock-to-out time.
LVCMOS18 (fast 16mA) clock-to-out time = 3.32ns - (2.43ns - 2.27ns) = 3.16ns
Is this correct?
----------------------------------------------------- Thanks, Bob