V-5 power saving ...how?

Hello! I'm trying to design in a V5, which will be sharing a memory bus with a DSP and some peripherals. However, the V5 consumes a lot of power (350 mW) when not doing anything, and so it would be nice to power it down (ala the Spartan-3L) in this mode.

Having looked at the app note and the comp.arch.fpga archives, it seems that simply shutting off all power to the FPGA could be problematic as this will leave the IO pins in an unknown state. So one suggested solution was :

tristate all IOBs
remove Vccaux and VCCint power
leave Vcco

thus keeping the IOs in a tri-state configuration.

From the XPower Estimator for the V5 it seems that quiescent power is

all made up of Vccint (239 mW) and VCCaux (118 mW) -- nothing for IO. Similarly, page 3 of DS202 (the DC/Switching data sheet for the V5) shows a XC5VLX30 sucking down a mere 1.5 mA @ VCCo (~ 5mW).

Is that -for the entire device- or per-bank? If per bank (ouch!) then I'm going to investigate using a coolrunner between the bus and the FPGA -- while it might hurt SI, it seems the only way.

What other schemes have people tried to reduce high-density device power consumption? Thanks,

...Eric

Jonas,

The static IO current is per bank (for 3.3V), in tristate, with pullups/pulldowns disabled.

2.5V, or 1.5V IO bank powering will be much less static current.

As soon as the Vccint, Vccaux, or Vcco_config supplies are below the power ON reset threshold, configuration memory (including BRAM is cleared), the device forces all IOs tristate (if there is a remaining Vcco supply). The IOs remain tristate until the POR is released when all of the three power supplies pass above their POR thresholds, the device has cleaned out, has configured, and the customer pattern has taken over control of the IOs (DONE goes high and it is all under your control).

If there is no power at all on any supply pins, then there is a diode from ground to an IO pin, and a diode from the IO pin to the Vcco pin (intrinsic self protecting output structure - ie "plain old CMOS totem pole" output structure).

Aust> Hello! I'm trying to design in a V5, which will be sharing a memory bus