Dear All,
I hope that you can help.
I am looking at trying to fit a number of IP cores into a single Xilinx FPGA, I have heard that it is not possible to completly utilise all the FPGA resources (RAM, Logic Cells, DCMs etc ... ) because of routing problems.
Do anyone know of a rough percentage of the the FPGA resources that can be expected to be utilised before issues arise in trying to route the design?
I have head that it is as low as 60% but am hoping that this is not the case.
I understand that it really does depend on what you put into the FPGA but to only be able to utilise 60% on average seams a little poor to me.
Kind Regards
Simon