I made use of two 1K*10B single port RAMs generated with coregen which is modified to contain my test vector, and P&R with that. However, I have one thousand test vector files in plain text to send to the FPGA one at a time.
I am wondering about whether I can write a perl script to manipulate the bitstream and generate an *incremental* bitstream so that I can avoid running ISE for one thousand times? Where can I find such information?
Thanks.