1. Home
  2. Field-Programmable Gate Arrays
  3. Using Sync Reset as Async Reset

Using Sync Reset as Async Reset

Hi @ all,

it is one possibility to synchronize an asynchronous reset so that all flip flops in the FPGA are resetted within the same clock period.

Using this synchronized reset can I still write the process like that:

process(Sync_reset, Clk) begin if Sync_reset='1' then ... elsif rising_edge(Clk) then ... end if;

end process;

or does it make more sense to write it like that:

process(Sync_reset, CLk) begin if rising_edge(Clk) then if Sync_reset='1' then ... else ... end if; end if; end process;

I would be very thankful for your opinion.

Rgds André

Reply to
ALuPin
Loading thread data ...

Your examples show exactly the difference between sync & async resets. Your 1st process will reset on the input, regardless of what the clock is doing. The synthesiser will use an asynchronous reset, if it's available. If it isn't, synthesis will (should?) fail.

Similarly, the 2nd process is synchronous, with clock governing reset. The synthesiser will use a synchronous reset, if it has one. If not, it will usually create one, by adding an AND gate right at the flipflop's input.

If you have g :Hi @ all, : :it is one possibility to :synchronize an asynchronous reset so that all flip flops in :the FPGA are resetted within the same clock period. : :Using this synchronized reset :can I still write the process like that: : : :process(Sync_reset, Clk) :begin : if Sync_reset='1' then : ... : elsif rising_edge(Clk) then : ... : end if; : :end process; : :or does it make more sense to write it like that: : :process(Sync_reset, CLk) :begin : if rising_edge(Clk) then : if Sync_reset='1' then : ... : else : ... : end if; : end if; :end process; : :I would be very thankful for your opinion. : :Rgds :André

Reply to
David R Brooks

There is a reason that the reset is async. If your clock goes away, you will not be able to reset the circuit with a purely synchronous reset. I normally use a combination, not in the entire chip, but on the critical portions. For example, I don't care how a data register powers up or what its timing is. But a FSM is important to power up correctly. But even then, not every FF has to be released at the same clock. If it is a one hot FSM, I use a two or three state init sequence that leads into my "normal" start state. This gives the async reset two or three clock cycles to propagate and release the rest of the FSM.

If you try to provide a sync reset to the entire chip in one clock cycle, you can burn a lot of routing resources and limit your clock speed.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX
Reply to
rickman

Confused about async./sync. resets? You should read this:

formatting link

Mostly ASIC related but most of it apply equally to FPGAs as well.

Regards, tore

Reply to
Tore Hansteen

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.